sab4z

Project information

A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

Xilinx Zynq VHDL Linux

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README
CeCILL Free Software License Agreement v2.1

Created on

March 30, 2017

Copy SSH clone URLgit@gitlab.enst.fr:renaud.pacalet/sab4z.git
Copy HTTPS clone URLhttps://gitlab.telecom-paris.fr/renaud.pacalet/sab4z.git

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