FPGA: The clock divider variable is not used on FPGA.
Right now in the Setting FPGA attributes user can see the "clock divider" field, but in fact there is no clock divider applied to FPGA. How clock divider should be used in FPGA?
Right now in the Setting FPGA attributes user can see the "clock divider" field, but in fact there is no clock divider applied to FPGA. How clock divider should be used in FPGA?