Disabling the cache may be an interesting option, at least during development, to force all load-store operations to cross the CPU boundary. When using the AXI simple bridge, the AXI bridge or even the SecBus HSM, it exposes much more memory accesses. There are probably other ways but this one works:
Modifying the Linux kernel to disable the caches
In your linux-xlnx working copy create a new version of arch/arm/configs/xilinx_zynq_defconfig and add some parameters to it:
Once the Linux kernel has booted one can check the CPU state to verify whether the caches are in use or not. This can be done by looking at the content of the SCTRL CPU register (using, for instance, a debugger through the JTAG port). Bits 12 and 2 of the SCTRL CPU register indicate whether the instruction and data caches are enabled, respectively. If these two bits are cleared (0), then all instruction and data caches are disabled.