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Fork from https://gitlab.inf.telecom-sudparis.eu/infra-web/hotcrp-docker.git

SystemVerilog simulation environment for an UART

This project contains the ontological framework developed during the MPM4CPS COST Action IC1404 () by working group 1 on foundations for MPM4CPS (http://mpm4cps.eu/).

QoE testbed for sampling constrained applications like Skype

A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

Yet another Makefile for LaTeX

This is a project of OPC UA specification Part 14 PubSub implementation.

The project include 2 major parts : OPC UA server with opc ua pubsub kit and OPC UA MQTT Configuration tool .

Matlab implementation associated with the article "On the use and denoising of the temporal geometric mean for SAR time series", submitted to IEEE Geoscience and Remote sensing Letters by N.Gasnier, L.Denis and F.Tupin.

Model synchronization between Adele and OSATE with MoTE TGG.

Python implementation of the GLRT based linear features detector proposed by N.Gasnier, L.Denis, and F.Tupin in Generalized Likelihood Ratio Tests for Linear Structure Detection in SAR Images (EUSAR 2021).

A hardware / software architecture protecting the external memories of an SoC