TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paristech.fr and @TTool_UML_SysML

RAMSES (Refinement of AADL Models for Synthesis of Embedded Systems) is a model transformation and code generation tool that produces C code for ARINC653-compliant operating systems and OSEK-compliant operating systems.

Modèle pour la génération de supports de cours (poly+slides) au format html, pdf et même docx à partir d'une source unique (au format markdown/pandooc).

API pour communication avec carte Mifare DESFire EV1

Modèle de présentation Beamer + Modèle de Poster aux couleur de TPT

simple python script to convert Synapses csv schedules to ics calendars.

A set of scripts and Makefiles for digital hardware projects

QoE testbed for sampling constrained applications like Skype

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

A simple example design for Zynq Ultrascale+ based boards.

Model synchronization between Adele and OSATE with MoTE TGG.

Présentation de l'offre de service de la DSI

Yet another Makefile for LaTeX

A perl utility to send data acquired by a sensor, through an Ethernet link (UDP packets), to a remote computer for real-time visualization with Gnuplot

TP!!!!!!!!

A hardware / software architecture protecting the external memories of an SoC