Explore projects

TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paris.fr and @TTool_UML_SysML

Nouveau thème Beamer aux couleur de Télécom Paris

RAMSES (Refinement of AADL Models for Synthesis of Embedded Systems) is a model transformation and code generation tool that produces C code for ARINC653-compliant operating systems and OSEK-compliant operating systems.

simple python script to convert Synapses csv schedules to ics calendars.

API pour communication avec carte Mifare DESFire EV1

Modèle pour la génération de supports de cours (poly+slides) au format html, pdf et même docx à partir d'une source unique (au format markdown/pandooc).

Experiment Specification (ExSpec) is a language to specify the provenance of experiment/simulation data. ExSpec models are the basis of the Validity Frame Language (VaFL, pronounced "waffle") to specify the validity frames of models.

Nouveau thème Beamer aux couleur de Télécom Paris

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

Alternate free software firmware for DFRobot DFR0592 DC motor driver hat

Modified version of QEMU for teaching (M2 SETI Embedded Linux, SE758 Linux Device Drivers...).