RAMSES (Refinement of AADL Models for Synthesis of Embedded Systems) is a model transformation and code generation tool that produces C code for ARINC653-compliant operating systems and OSEK-compliant operating systems.

TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paristech.fr and @TTool_UML_SysML

API pour communication avec carte Mifare DESFire EV1

Modèle pour la génération de supports de cours (poly+slides) au format html, pdf et même docx à partir d'une source unique (au format markdown/pandooc).

Modèle de présentation Beamer + Modèle de Poster aux couleur de TPT

simple python script to convert Synapses csv schedules to ics calendars.

Yet another Makefile for LaTeX

A simple example design for Zynq Ultrascale+ based boards.

A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

This project provides utility libraries that can be used by several MBE tools such as RAMSES, TTool or RDALTE

Présentation de l'offre de service de la DSI

A set of scripts and Makefiles for digital hardware projects

Model synchronization between Adele and OSATE with MoTE TGG.

QoE testbed for sampling constrained applications like Skype

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator