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RAMSES-2 (Refinement of AADL Models for Synthesis of Embedded Systems) is a model refinement and code generation tool that produces C code for ARINC653, OSEK and POSIX-compliant operating systems. More at https://mem4csd.telecom-paristech.fr/blog/

simple python script to convert Synapses csv schedules to ics calendars.

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

This is the repository containing the code of the PEPR - PC7 project

Alternate free software firmware for DFRobot DFR0592 DC motor driver hat

A Benchmark of Incremental Model Transformation Tools based on an Industrial Case Study with AADL

Compagnon repository of the paper 'Invariance-based semi-supervised representation learning for sound event detection'.

Generation of SystemC code from AADL models for functional simulation