Explore projects

A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

Fork from https://gitlab.inf.telecom-sudparis.eu/infra-web/hotcrp-docker.git

Nouveau thème Beamer aux couleur de Télécom Paris

RAMSES (Refinement of AADL Models for Synthesis of Embedded Systems) is a model transformation and code generation tool that produces C code for ARINC653-compliant operating systems and OSEK-compliant operating systems.

Yet another Makefile for LaTeX

SAR Image Despeckling by Deep Neural Networks: from a pre-trained model to an end-to-end training strategy - Notebook implementation usable on Google Colaboratory