In this commit I have done:
- Fix FPGA scheduling: One can map several tasks on a FPGA. We can execute all these tasks together, or execute groups of tasks one after the other. For instance, if we map T1, T2, T3, T4, T5 on the FPGA, a user can specify T1 T2 ; T3 ; T4 T5 which means than T1 and T2 are first executed until they terminate. Then T3. Then T4 and T5. Note that if two tasks are connected with the same channel they should have the same scheduling (same priority).
- Remove redundant white space between FPGA and displayed tasks at first.
- Add tests for rescheduling of FPGA.
- I have an idea about scaling the timeline diagram: I will divide the length of each transactions to a predefined factor so the scale between each transactions remain the same. I will try to submit it on the next merger request.