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readme_avatardeployment

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    readme_avatardeployment 5.78 KiB
    Installation for Linux and MacOSX: 
    ==================================
    System preconditions : 
    1) You have to obtain TTool from the Telecom site. This is usually already done
    as this readme is includes in TTool.
    
    2) You have to obtain the Prog arborescence from the svn containing MutekH and a SoClib platform
    
    3) Your system has to feature a gcc compiler and a gdb
    
    - Linux : gcc 4.7. was tested with success but is not he most recent
    - MacOSX : there are some difficulties with MacOSX, we recommend the homebrew gcc-4.8 compiler
    
    4) The crosscompiler will serve to compile your application (the task and main file produced by TTool)
       for the desired architecture.
       To generate your crosscompilers, you have to execute ./crossgen.mk in
      the Prog/mutekh directory. Usually type 
      ./crossgen.mk all 
      the first time 
      Currently only PowerPC is available, but it is relatively easy to add others as MutekH
      allows heterogeneous processors - the topcell is written in a way
      that it works for the following :  
    
      ppc405
      niosII
      mips32
      arm.h
      sparcv8.h
      lm32.h
    
    5) You have to have a valid SystemC compiler to compile the SoCLib platform
    
    - Linux : systemc-2.2.0 was tested
    - MacOSX : systemc-2.3.1 from Accellera was tested with success; here is the link : accellera.org/downloads/standards/systemc
    
    SystemCASS also works, libraries for Linux are contained in the distribution
    
    -------------------------------------------------------------------------------
    Additions to the TTool arborescence:
    ====================================
    
    at top level, a directory named  MPSoC was added: 
    
    - generated_src: generated task code for AVATAR blocks and main code spawning the POSIX threads
    - src : the runtime for MPSoC platforms (using mwmr channels)
    - generated_topcell: topcell and mapping information to generate the ldscript
    
    --------------------------------------------------------------------
    TTool will copy code from these directories into the Prog arborescence as follows:
    
    generated_src :  *.c and *h to Prog/mutekh/examples/avatar
    		      src_soclib to Prog/mutekh/libavatar
    
    generated_topcell :
    		  top.cc to  ~/Prog/soclib/soclib/platform/topcells/caba-vgmn-mutekh_kernel_tutorial/top.cc
    		 deployinfo.h and deployinfo_map.h to ~/Prog/mutekh/arc/soclib
                     they are used by ldscrot.cpp, a preprocessor generating the ldscript
    
    -------------------------------------------------------------
    Using TTool/AVATAR with SoCLib
    -------------------------------------------------------------
    Code Generation from Deployment Diagrams
    
    In the src directory, ddtranslatorSoclib was added, which analyzed the deployment diagram
    it contains subdirectories toSoclib and toTopCell generating task/main code and topcell/information for the 
    ldscript and main, respectively
    Other files from TTool had to be slightly adapted, not listed here
    
    --------------------------------------------------------------------------------------
    In TURTLE/bin/ you may add the following two lines in the config.xml file :
    
    <AVATARMPSoCCodeDirectory data="/users/enseig/genius/TURTLE/MPSoC/" />
    <AVATARMPSoCCompileCommand data="make -C /users/enseig/genius/TURTLE/MPSoC updategeneratedcode compilesoclib" />
    
    ---------------------------------------------------------------------------------
    Summary: how to use Deployment Diagrams (awaiting a detailed tutorial)
    ======================================================================
    
    These features are available in the experimental version; the option -experimental
    must be added in ttool.exe for example
    
    java -Xmx1024m -Djavax.net.ssl.trustStore=ServerKeyStore -Djavax.net.ssl.trustStorePassword=123456  -jar ttool.jar -config config.xml -experimental -debug -avatar -uppaal -launcher 
    
    
    When starting from an existing diagram : automatically opened together with AVATAR diagram (File->open)
    
    - Click on AVATAR Design (left tab in main window)
      select V&V then Syntax Analysis; this reads in the diagrams and checks their syntax
    - Click on AvatarDeployment (right tab in main window) 
      Click on the gear at the right of the lower toolbar (Deployment Diagram toolbar)
    
    - select AVATAR SOCLIB code generator in the code generation menu (only one option available if generating code with deployment)
      it is recommended to select the debug option to have detailed output
      tracing is currently not active but cycle information can be obtained
    - select Compile tab, then "Compile soclib executable with" then "Start" in the compile menu
    - select Execute tab, then "Run code in soclib/mutekh" then "Start" in the Exeute menu
    
    A TTY (green on black) should open; if the debug option was selected, the
    application progress and read/write operation on channels can be monitored 
    (this is provisional awaiting more comfortable tracing facilities on cycle accurate level)
    
    Designing one's own diagrams: 
    
    ight click on Avatar Deployment tab : New AVATAR Deployment Diagram
    
    toolbar in the Deployment Diagram tab (lower toolbar)
    The following components are available
    
    CPU
    task to CPU: map tasks onto processors
    DMA: not yet implemented
    ICU: currently transparently present in all platforms
    COPROCESSOR: not yet implemented
    TIMER: not yet implemented
    TTY
    BUS
    BRIDGE: not yet implemented
    VGMN
    CROSSBAR : implemented but no hierarchy yet
    RAM
    Channel to RAM : map channels onto memory banks
    ROM
    
    "not yet implemented" = exists in AVATAR, but corresponding SoCLib component is not yet taken into account 
    in the platform generation
    
    hardware components have to be connected by arcs (fourth from the left) to the interconnect
    one level of interconnect, either VGMN, bus (VGSB) or Crossbar supported currently
    
    Right click on components then select edit allows to modify attributes : for example, specify number of cache lines,
    the size of a memory bank
    --------------------------------------------------------------------------------------------
    Please contact daniela.genius@lip6.fr