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Commit 13491ed4 authored by Irina LEE's avatar Irina LEE
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delete toSysCAMS files

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src/main/java/syscamstranslator/toSysCAMS/Declaration.java deleted 100644 → 0
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/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
* Daniela Genius, Lip6, UMR 7606
*
* ludovic.apvrille AT enst.fr
* daniela.genius@lip6.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*/
/* authors: v1.0 Raja GATGOUT 2014
v2.0 Daniela GENIUS, Julien HENON 2015
v2.1 Daniela GENIUS, 2016, 2017 */
package ddtranslatorSoclib.toTopCell;
import ddtranslatorSoclib.*;
import avatartranslator.AvatarRelation;
import avatartranslator.AvatarBlock;
import avatartranslator.AvatarSignal;
import avatartranslator.AvatarSpecification;
public class Declaration {
public static AvatarSpecification avspec;
private static String CR = "\n";
private static String CR2 = "\n\n";
public static String generateName(AvatarRelation _ar, int _index) {
return _ar.block1.getName() + "_" + _ar.getSignal1(_index).getName() + "__" + _ar.block2.getName() + "_"
+ _ar.getSignal2(_index).getName();
}
public static String getDeclarations(AvatarSpecification _avspec) {
avspec = _avspec;
String declaration = "//----------------------------Instantiation-------------------------------" + CR2;
int nb_clusters = TopCellGenerator.syscams.getAllCrossbar().size();
boolean trace_caba = true;
if (nb_clusters == 0) {
declaration += CR + "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0), maptab);"
+ CR;
} else {
declaration += CR + "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0,0), maptab);"
+ CR;
}
if (nb_clusters == 0) {
declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(1), maptab, data_ldr);" + CR;
} else {
declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(0,1), maptab, data_ldr);" + CR;
}
if (nb_clusters == 0) {
declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(3), maptab);" + CR;
} else {
declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(0,3), maptab);"
+ CR;
}
if (nb_clusters == 0) {
declaration = declaration
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ CR;
} else {
declaration = declaration
+ "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());"
+ CR;
}
if (nb_clusters == 0) {
declaration = declaration
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(5), maptab, 1, true);" + CR2;
} else {
declaration = declaration
+ "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);" + CR2;
}
if (nb_clusters == 0) {
declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);" + CR;
} else {
declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);" + CR;
}
int last_tty = 0;
if (nb_clusters == 0) {
int i = 0;
for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName() + "(\"" + tty.getTTYName()
+ "\", IntTab(" + tty.getNo_target() + "), maptab, \"vci_multi_tty" + i + "\", NULL);" + CR;
i++;
last_tty = tty.getNo_target() + 1;
}
// target address depends on number of TTYs and RAMs
if (nb_clusters == 0) {
// declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\",
// IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(" + (last_tty + 3)
+ "), maptab);" + CR;
} else {
declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
}
for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM())
if (ram.getIndex() == 0) {
declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName() + "(\"" + ram.getMemoryName()
+ "\"" + ", IntTab(2), maptab);" + CR;
} else {
declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName() + "(\"" + ram.getMemoryName()
+ "\"" + ", IntTab(" + ram.getNo_target() + "), maptab);" + CR;
}
} else {
int i = 0;
for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName() + "(\"" + tty.getTTYName()
+ "\", IntTab(" + tty.getNo_cluster() + "," + tty.getNo_target() + "), maptab, \"vci_multi_tty"
+ i + "\", NULL);" + CR;
i++;
}
for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM())
declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName() + "(\"" + ram.getMemoryName()
+ "\"" + ", IntTab(" + ram.getNo_cluster() + "," + ram.getNo_target() + "), maptab);" + CR2;
}
if (nb_clusters == 0) {
/*
* declaration +=
* "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("
* +(TopCellGenerator.avatardd.getNb_target())+"));" + CR; declaration +=
* "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("
* +(TopCellGenerator.avatardd.getNb_target()+1)+"), \"soclib0\");" + CR;
* declaration +=
* "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("
* +(TopCellGenerator.avatardd.getNb_target()+2)+"),\"block0.iso\", 2048);" +
* CR;
*/
declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("
+ last_tty + "));" + CR;
declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("
+ (last_tty + 1) + "), \"soclib0\");" + CR;
declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("
+ (last_tty + 2) + "),\"block0.iso\", 2048);" + CR;
// only non-clustered version
int hwa_no = 0;
// int target_no = TopCellGenerator.avatardd.getNb_target();
int target_no = (last_tty + 4);// DG 5.9.
int init_no = TopCellGenerator.syscams.getNb_init();
for (AvatarCoproMWMR copro : TopCellGenerator.syscams.getAllCoproMWMR()) {
// declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+
// "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "),
// IntTab("+copro.getTgtid() +
// "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(),
// copro.getUseLLSC());"+ CR;
declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName() + "(\""
+ copro.getCoprocName() + "\", maptab, IntTab(" + (init_no - 1) + "), IntTab(" + target_no
+ ")," + copro.getPlaps() + "," + copro.getFifoToCoprocDepth() + ","
+ copro.getFifoFromCoprocDepth() + "," + copro.getNToCopro() + "," + copro.getNFromCopro() + ","
+ copro.getNConfig() + "," + copro.getNStatus() + "," + copro.getUseLLSC() + ");" + CR2;
// one virtual component for each hardware accellerator, info from diplodocus
// (not yet implemented)
// DG 28.08.
// declaration += "soclib::caba::FifoVirtualCoprocessorWrapper
// hwa"+hwa_no+"(\"hwa"+hwa_no+"\",1,1,1,1);"+ CR2;
declaration += "dsx::caba::MyHWA" + hwa_no + " hwa" + hwa_no + "(\"hwa" + hwa_no + "\");" + CR2;
target_no++;
init_no++;
hwa_no++;
}
} else {
declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));"
+ CR;
declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");"
+ CR;
declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);"
+ CR;
}
if (nb_clusters == 0) {
for (AvatarBus bus : TopCellGenerator.syscams.getAllBus()) {
System.out.println("initiators: " + TopCellGenerator.syscams.getNb_init());
System.out.println("targets: " + TopCellGenerator.syscams.getNb_target());
// declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName()
// + "\"" + " , maptab, cpus.size()+3," +
// (TopCellGenerator.avatardd.getNb_target()+4)+");" + CR2;
// declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName()
// + "\"" + " , maptab, cpus.size()+3," +
// (TopCellGenerator.avatardd.getNb_target()+4)+ ");" + CR2;
declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab,"
+ (3 + TopCellGenerator.syscams.getNb_init()) + ","
+ (TopCellGenerator.syscams.getNb_target() + 4) + ");" + CR2;// DG 28.08.
int i = 0;
// if BUS was not last in input file, update here
bus.setNbOfAttachedInitiators(TopCellGenerator.syscams.getNb_init());
bus.setnbOfAttachedTargets(TopCellGenerator.syscams.getNb_target());
}
for (AvatarVgmn vgmn : TopCellGenerator.syscams.getAllVgmn()) {
// System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
// System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
/*
* The user might have forgotten to specify the following, thus set default
* values
*/
if (vgmn.getMinLatency() < 2)
vgmn.setMinLatency(10); // default value; must be > 2
if (vgmn.getFifoDepth() < 2)
vgmn.setFifoDepth(8); // default value; must be > 2
// declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
// vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," +
// (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() +
// "," + vgmn.getFifoDepth() + ");" + CR2;
// declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
// vgmn.getVgmnName() + "\"" + " , maptab, "
// +(3+TopCellGenerator.avatardd.getNb_init())+"," +
// (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() +
// "," + vgmn.getFifoDepth() + ");" + CR2;//DG 28.08.
declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, "
+ (3 + TopCellGenerator.syscams.getNb_init()) + ","
+ (TopCellGenerator.syscams.getNb_target() + 3) + "," + vgmn.getMinLatency() + ","
+ vgmn.getFifoDepth() + ");" + CR2;// DG 5.9.
// declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" +
// vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," +
// (TopCellGenerator.avatardd.getNbRAM()+TopCellGenerator.avatardd.getNbTTY()+4)+
// "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
// if VGMN was not last in input file, update here
vgmn.setNbOfAttachedInitiators(TopCellGenerator.syscams.getNb_init());
vgmn.setnbOfAttachedTargets(TopCellGenerator.syscams.getNb_target() + 4);
}
/*
* VciMwmrController( sc_module_name name, const MappingTable &mt, const IntTab
* &srcid, const IntTab &tgtid, const size_t plaps, const size_t
* fifo_to_coproc_depth, const size_t fifo_from_coproc_depth, const size_t
* n_to_coproc, const size_t n_from_coproc, const size_t n_config, const size_t
* n_status, const bool use_llsc );
*/
} else {
/***************************************/
/* clustered interconnect architecture */
/***************************************/
for (AvatarBus bus : TopCellGenerator.syscams.getAllBus()) {
declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, "
+ +nb_clusters + "," + nb_clusters + ");" + CR2;
// if BUS was not last in input file, update here
int i = 0;
}
for (AvatarVgmn vgmn : TopCellGenerator.syscams.getAllVgmn()) {
System.out.println("initiators: " + TopCellGenerator.syscams.getNb_init());
System.out.println("targets: " + TopCellGenerator.syscams.getNb_target());
declaration += "soclib::caba::VciVgmn<vci_param> vgmn (\"" + vgmn.getVgmnName() + "\"" + " , maptab, "
+ nb_clusters + "," + nb_clusters + "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth()
+ ");" + CR2;
}
int i = 0;
for (AvatarCrossbar crossbar : TopCellGenerator.syscams.getAllCrossbar()) {
// currently the number on initiators and targets is fixed
crossbar.setClusterIndex(i);
if (crossbar.getClusterIndex() == 0) {
crossbar.setNbOfAttachedInitiators(nb_clusters);
crossbar.setNbOfAttachedTargets(13);
} else {
// processor(s) and link to central interconnect are initiators
// crossbar.setNbOfAttachedInitiators(2);
// crossbar.setNbOfAttachedTargets(2);
crossbar.setNbOfAttachedInitiators(1);
crossbar.setNbOfAttachedTargets(1);
}
System.out.println("initiators: " + crossbar.getNbOfAttachedInitiators());
System.out.println("targets: " + crossbar.getNbOfAttachedTargets());
declaration += "soclib::caba::VciLocalCrossbar<vci_param> crossbar" + crossbar.getClusterIndex() + "(\""
+ crossbar.getCrossbarName() + "\"" + " , maptab, IntTab(" + crossbar.getClusterIndex()
+ "),IntTab(" + crossbar.getClusterIndex() + "), " + crossbar.getNbOfAttachedInitiators() + ", "
+ crossbar.getNbOfAttachedTargets() + ");" + CR2;
// if CROSSBAR was not last in input file, update here
crossbar.setNbOfAttachedInitiators(TopCellGenerator.syscams.getNb_init());
crossbar.setNbOfAttachedTargets(TopCellGenerator.syscams.getNb_target());
}
}
int i = 0;
// monitoring CPU by logger(1)
for (AvatarCPU cpu : TopCellGenerator.syscams.getAllCPU()) {
if (cpu.getMonitored() == 1) {
System.out.println("Spy CPU");
declaration += "soclib::caba::VciLogger<vci_param> logger" + i + "(\"logger" + i + "\",maptab);" + CR2;
i++;
}
}
int j = 0;
// monitoring RAM either by logger(1) ou stats (2)
for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM()) {
if (ram.getMonitored() == 0) {
}
if (ram.getMonitored() == 1) {
System.out.println("Spy RAM : Logger");
declaration += "soclib::caba::VciLogger<vci_param> logger" + i + "(\"logger" + i + "\",maptab);" + CR2;
i++;
} else {
if (ram.getMonitored() == 2) {
System.out.println("Spy RAM : Stats");
String strArray = "";
for (AvatarRelation ar : avspec.getRelations()) {
for (i = 0; i < ar.nbOfSignals(); i++) {
AvatarSignal as1 = ar.getSignal1(i);
AvatarSignal as2 = ar.getSignal2(i);
String chname = generateName(ar, i);
strArray = strArray + "\"" + chname + "\",";
}
}
declaration += "soclib::caba::VciMwmrStats<vci_param> mwmr_stats" + j + "(\"mwmr_stats" + j
+ "\",maptab, data_ldr, \"mwmr" + j + ".log\",stringArray(" + strArray + "NULL));" + CR2;
j++;
}
}
}
return declaration;
}
}
\ No newline at end of file
src/main/java/syscamstranslator/toSysCAMS/Loader.java deleted 100644 → 0
+ 0
− 148
View file @ 381c009b
/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
* Daniela Genius, Lip6, UMR 7606
*
* ludovic.apvrille AT enst.fr
* daniela.genius@lip6.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*/
/* authors: v1.0 Daniela GENIUS, Julien HENON 2015 */
package ddtranslatorSoclib.toTopCell;
import avatartranslator.AvatarRelation;//DG 23.06.
import avatartranslator.AvatarSpecification;//DG 23.06.
import ddtranslatorSoclib.AvatarChannel;
public class Loader {
public static AvatarSpecification avspec;
static private String loader;
private final static String NAME_CLK = "signal_clk";
private final static String CR = "\n";
private final static String CR2 = "\n\n";
public Loader(AvatarSpecification _avspec){
avspec =_avspec;
}
public static String getLoader(AvatarSpecification _avspec) {//DG 23.06.
avspec =_avspec;//DG 23.06.
int nb_clusters=TopCellGenerator.syscams.getAllCrossbar().size();
//nb_clusters=2;
loader = CR2 + "//-------------------------Call Loader---------------------------------" + CR2 ;
loader = loader + "std::cerr << \"caba-vgmn-mutekh_kernel_tutorial SoCLib simulator for MutekH\" << std::endl;"
+ CR2 ;
loader = loader + "if ( (argc < 2) || ((argc % 2) == 0) ) {" + CR ;
loader = loader + "exit(0); }" + CR ;
loader = loader + " argc--;" + CR ;
loader = loader + " argv++;" + CR2 ;
loader = loader + "bool heterogeneous = (argc > 2);" + CR2 ;
loader = loader + " for (int i = 0; i < (argc - 1); i += 2){" + CR ;
loader = loader + " char *cpu_p = argv[i];" + CR ;
loader = loader + " const char *kernel_p = argv[i+1];" + CR ;
loader = loader + " const char *arch_str = strsep(&cpu_p, \":\");" + CR ;
loader = loader + " int count = cpu_p ? atoi(cpu_p) : 1;" + CR ;
loader = loader + " common::Loader *text_ldr; " + CR ;
loader = loader + " if (heterogeneous) {" + CR ;
loader = loader + " text_ldr = new common::Loader(std::string(kernel_p) + \";.text\");" + CR ;
loader = loader + " text_ldr->memory_default(0x5a);;" + CR ;
loader = loader + " data_ldr.load_file(std::string(kernel_p) + \";.rodata;.boot;.excep\");" + CR ;
loader = loader + " if (i == 0)" + CR ;
loader = loader + " data_ldr.load_file(std::string(kernel_p) + \";.data;";
// We generated so far until arriving at first channel segment, if any
//current hypothesis : one segment per channel
int j=0;
//for (AvatarChannel channel : TopCellGenerator.avatardd.getAllMappedChannels()) {
//DG 23.06. per signal!!hack pour l'instant
int i=0;
//for (i=0;i<30;i++){
for(AvatarRelation ar: avspec.getRelations()) {
for(i=0; i<ar.nbOfSignals() ; i++) {
loader = loader + ".channel" + j + ";";
j++;
}
}
// We resume the generation of the fixed code
loader = loader + ".cpudata;.contextdata\");" + CR ;
loader = loader + " } else {" + CR ;
loader = loader + " text_ldr = new common::Loader(std::string(kernel_p));" + CR ;
loader = loader + " text_ldr->memory_default(0x5a);" + CR ;
loader = loader + " data_ldr.load_file(std::string(kernel_p));" + CR ;
loader = loader + " }" + CR2 ;
loader = loader + " common::Loader tools_ldr(kernel_p);" + CR ;
loader = loader + " tools_ldr.memory_default(0x5a);" + CR2 ;
loader = loader + " for (int j = 0; j < count; j++) {" + CR ;
loader = loader + " int id = cpus.size();" + CR ;
loader = loader + " std::cerr << \"***\" << cpus.size() << std::endl;" + CR ;
loader = loader + " CpuEntry *e = newCpuEntry(arch_str, id, text_ldr);" + CR ;
loader = loader + " if (j == 0)" + CR ;
loader = loader + " e->init_tools(tools_ldr);" + CR ;
loader = loader + " e->cpu = e->new_cpu(e);" + CR ;
loader = loader + " cpus.push_back(e);" + CR ;
loader = loader + " }" + CR ;
loader = loader + " }" + CR2 ;
int nb_tty =1; //DG currently only one (multi) tty
if(nb_clusters==0){
loader = loader + " const size_t xicu_n_irq = "+(1+nb_tty+3)+";" + CR2 ;
}else{
loader = loader + " const size_t xicu_n_irq = "+(5*nb_clusters)+";" + CR2 ;
}
return loader;
}
String getNAME_CLK(){
return NAME_CLK;
}
}
src/main/java/syscamstranslator/toSysCAMS/NetList.java deleted 100644 → 0
+ 0
− 508
View file @ 381c009b
This diff is collapsed.
src/main/java/syscamstranslator/toSysCAMS/PrimitiveCode.java
+ 2
− 2
View file @ 13491ed4
...@@ -61,8 +61,8 @@ import ui.syscams.SysCAMSPortTDF; ...@@ -61,8 +61,8 @@ import ui.syscams.SysCAMSPortTDF;
*/ */
public class PrimitiveCode { public class PrimitiveCode {
static private String corpsPrimitive; private String corpsPrimitive;
static private String corpsCluster; private String corpsCluster;
private final static String CR = "\n"; private final static String CR = "\n";
private final static String CR2 = "\n\n"; private final static String CR2 = "\n\n";
......
src/main/java/syscamstranslator/toSysCAMS/Signal.java deleted 100644 → 0
+ 0
− 163
View file @ 381c009b
/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
* Daniela Genius, Lip6, UMR 7606
*
* ludovic.apvrille AT enst.fr
* daniela.genius@lip6.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*/
/* This class generates the lines of the topcell where the signals are declared*/
/* authors: v1.0 Raja GATGOUT 2014
v2.0 Daniela GENIUS, Julien HENON 2015 */
package ddtranslatorSoclib.toTopCell;
import ddtranslatorSoclib.AvatarCoproMWMR;
import ddtranslatorSoclib.AvatarRAM;
import ddtranslatorSoclib.AvatarTTY;
public class Signal {
private final static String CR = "\n";
private final static String CR2 = "\n\n";
private final static String NAME_CLK = "signal_clk";
private static final String NAME_RST = "signal_resetn";
public static String getSignal() {
int nb_clusters = TopCellGenerator.syscams.getAllCrossbar().size();
// nb_clusters=2;
String signal = CR2 + "//-------------------------------signaux------------------------------------" + CR2;
signal = signal + "caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_xicu(\"signal_vci_xicu\");" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdtrom(\"signal_vci_vcifdtrom\");" + CR;
signal = signal + " caba::VciSignals<vci_param> signal_vci_vcihetrom(\"signal_vci_vcihetrom\");" + CR;
signal = signal + " caba::VciSignals<vci_param> signal_vci_vcirom(\"signal_vci_vcirom\");" + CR;
signal = signal + " caba::VciSignals<vci_param> signal_vci_vcisimhelper(\"signal_vci_vcisimhelper\");" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_vcirttimer(\"signal_vci_vcirttimer\");" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_vcilocks(\"signal_vci_vcilocks\");" + CR;
// signal = signal +"caba::VciSignals<vci_param>
// signal_vci_mwmr_ram(\"signal_vci_mwmr_ram\");"+ CR;
// signal = signal +"caba::VciSignals<vci_param>
// signal_vci_mwmrd_ram(\"signal_vci_mwmrd_ram\");"+ CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdaccessi;" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdaccesst;" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_bdi;" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_bdt;" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_etherneti;" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_ethernett;" + CR;
signal = signal + "" + CR;
signal = signal + "sc_clock signal_clk(\"signal_clk\");" + CR;
signal = signal + "sc_signal<bool> signal_resetn(\"" + NAME_RST + "\");" + CR2;
int i = 0;
for (AvatarCoproMWMR copro : TopCellGenerator.syscams.getAllCoproMWMR()) {
signal = signal + "caba::VciSignals<vci_param> signal_mwmr_" + i + "_initiator;" + CR;
signal = signal + "caba::VciSignals<vci_param> signal_mwmr_" + i + "_target;" + CR;
signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_" + i + "_from_ctrl;" + CR;
signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_" + i + "_to_ctrl;" + CR;
i++;
}
if (TopCellGenerator.syscams.getAllCrossbar().size() == 0) {
for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM())
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2;
i = 0;
for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
// signal = signal + "soclib::caba::VciSignals<vci_param>
// signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" +
// CR2;
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty" + i + "(\"signal_vci_tty" + i
+ "\");" + CR2;
i++;
}
signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
System.out.print("number of processors : " + TopCellGenerator.syscams.getNbCPU() + "\n");
}
else {
for (AvatarRAM ram : TopCellGenerator.syscams.getAllRAM())
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2;
i = 0;
for (AvatarTTY tty : TopCellGenerator.syscams.getAllTTY()) {
// signal = signal + "soclib::caba::VciSignals<vci_param>
// signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" +
// CR2;
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty" + i + "(\"signal_vci_tty" + i
+ "\");" + CR2;
i++;
}
int p = 0;
// if (with_hw_accellerator>0){ //DG 23.08.
for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.syscams.getAllCoproMWMR()) {
// les accellerateurs sont caches car apparaissent uniquement au niveau
// DIPLODOCUS
// signal = signal + " soclib::caba::VciSignals<vci_param>
// signal_mwmr"+HWAccelerator.getNo()+"_target(\"signal_mwmr"+HWAccelerator.getNo()+"_target\""+CR;
// signal = signal + " soclib::caba::VciSignals<vci_param>
// signal_mwmr"+HWAccelerator.getNo()+"_initiator(\"signal_mwmr"+HWAccelerator.getNo()+"_initiator\""
// +CR;
// signal = signal + " soclib::caba::FifoSignals<uint32_t>
// signal_fifo_to_ctrl"+HWAccelerator.getNo()+"(\"signal_fifo_to_ctrl"+HWAccelerator.getNo()+"\");"+CR;
// signal = signal + " soclib::caba::FifoSignals<uint32_t>
// signal_fifo_from_ctrl"+HWAccelerator.getNo()+"(\"signal_fifo_from_ctrl"+HWAccelerator.getNo()+"\");"+CR;
signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr" + p + "_target(\"signal_mwmr" + p
+ "_target\"" + CR;
signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr" + p + "_initiator(\"signal_mwmr"
+ p + "_initiator\"" + CR;
signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_to_ctrl" + p
+ "(\"signal_fifo_to_ctrl" + p + "\");" + CR;
signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_from_ctrl" + p
+ "(\"signal_fifo_from_ctrl" + p + "\");" + CR;
p++;
}
signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
// System.out.print("number of processors : " +
// TopCellGenerator.avatardd.getNbCPU()+"\n");
System.out.print("number of clusters : " + TopCellGenerator.syscams.getNbClusters() + "\n");
}
return signal;
}
}
src/main/java/syscamstranslator/toSysCAMS/Simulation.java deleted 100644 → 0
+ 0
− 74
View file @ 381c009b
/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
* Daniela Genius, Lip6, UMR 7606
*
* ludovic.apvrille AT enst.fr
* daniela.genius@lip6.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*/
/* authors: v1.0 Raja GATGOUT 2014
v2.0 Daniela GENIUS, Julien HENON 2015 */
package ddtranslatorSoclib.toTopCell;
public class Simulation {
private static String simulation;
private final static String CR = "\n";
private final static String CR2 = "\n\n";
public Simulation(){
}
public static String getSimulation(){
simulation = CR2+ CR2+
"/***************************************************************************" + CR +
"----------------------------simulation-------------------------" + CR +
"***************************************************************************/"+CR2 ;
simulation =simulation+"int sc_main (int argc, char *argv[])" + CR + "{" + CR;
simulation = simulation +" try {" + CR +" return _main(argc, argv);" + CR + " }" + CR2;
simulation =simulation +" catch (std::exception &e) {" + CR + " std::cout << e.what() << std::endl;" + CR + " throw;"+ CR+" }";
simulation =simulation+" catch (...) {" + CR;
simulation =simulation+"std::cout << \"Unknown exception occured\" << std::endl;" + CR;
simulation =simulation+"throw;" + CR;
simulation =simulation+"}" + CR;
simulation = simulation+ CR +" return 1;"+ CR + "}" ;
return simulation;
}
}
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