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mbe-tools
TTool
Commits
313258ae
Commit
313258ae
authored
5 years ago
by
Le Van Truong
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add test for read and write active delay parameter on TML
parent
f4c34194
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2 merge requests
!261
Revert c7faf42b
,
!259
Revert c7faf42b
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1 changed file
ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java
+195
-2
195 additions, 2 deletions
ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java
with
195 additions
and
2 deletions
ttool/src/test/java/tmltranslator/DiplodocusDelayTest.java
+
195
−
2
View file @
313258ae
...
...
@@ -9,6 +9,7 @@ import org.junit.BeforeClass;
import
org.junit.Test
;
import
req.ebrdd.EBRDD
;
import
tepe.TEPE
;
import
tmltranslator.compareTMLTest.CompareTML
;
import
tmltranslator.tomappingsystemc2.DiploSimulatorFactory
;
import
tmltranslator.tomappingsystemc2.IDiploSimulatorCodeGenerator
;
import
tmltranslator.tomappingsystemc2.Penalties
;
...
...
@@ -41,8 +42,13 @@ public class DiplodocusDelayTest extends AbstractUITest {
final
int
[]
NB_Of_DELAY_TRANSTIONS_PENALTIES
=
{
41
,
41
,
41
,
41
,
31
,
21
};
final
int
[]
MIN_DELAY_CYCLES_PENALTIES
=
{
2590
,
2590
,
2670
,
2670
,
2010
,
1950
};
final
int
[]
MAX_DELAY_CYCLES_PENALTIES
=
{
2590
,
2590
,
2670
,
2670
,
2010
,
1950
};
// test for read and write active delay parameter
final
String
[]
MODELS_DELAY_READ_WRITE
=
{
"delayRW"
};
final
static
String
EXPECTED_FILE1
=
getBaseResourcesDir
()
+
"tmltranslator/expected/expected_specdelay_readwrite.tml"
;
final
int
[]
NB_Of_DELAY_RW_STATES
=
{
42
};
final
int
[]
NB_Of_DELAY_RW_TRANSTIONS
=
{
41
};
final
int
[]
MIN_DELAY_RW_CYCLES
=
{
2020
};
final
int
[]
MAX_DELAY_RW_CYCLES
=
{
2020
};
private
String
SIM_DIR
;
...
...
@@ -372,5 +378,192 @@ public class DiplodocusDelayTest extends AbstractUITest {
assertTrue
(
MAX_DELAY_CYCLES_PENALTIES
[
i
]
==
maxValue
);
}
}
@Test
public
void
testGenerateTML
()
throws
Exception
{
CompareTML
compTML
=
new
CompareTML
();
mainGUI
.
openProjectFromFile
(
new
File
(
RESOURCES_DIR
+
"delay-readwrite.xml"
));
for
(
TURTLEPanel
_tab
:
mainGUI
.
getTabs
())
{
if
(
_tab
instanceof
TMLArchiPanel
)
{
for
(
TDiagramPanel
tdp
:
_tab
.
getPanels
())
{
if
(
tdp
instanceof
TMLArchiDiagramPanel
)
{
mainGUI
.
selectTab
(
tdp
);
break
;
}
}
break
;
}
}
mainGUI
.
checkModelingSyntax
(
true
);
mainGUI
.
generateTMLTxt
();
File
f1
=
new
File
(
EXPECTED_FILE1
);
File
f2
=
new
File
(
"spec.tml"
);
// Generated file after executing "TML generation"
assertTrue
(
compTML
.
compareTML
(
f1
,
f2
));
}
@Test
public
void
testActiveDelayReadAndWrite
()
throws
Exception
{
for
(
int
i
=
0
;
i
<
MODELS_DELAY_READ_WRITE
.
length
;
i
++)
{
String
s
=
MODELS_DELAY_READ_WRITE
[
i
];
SIM_DIR
=
DIR_GEN
+
s
+
"/"
;
// Load the TML
System
.
out
.
println
(
"executing: loading "
+
s
);
TMLMappingTextSpecification
tmts
=
new
TMLMappingTextSpecification
(
s
);
File
f
=
new
File
(
RESOURCES_DIR
+
s
+
".tmap"
);
System
.
out
.
println
(
"executing: new file loaded "
+
s
);
String
spec
=
null
;
try
{
spec
=
FileUtils
.
loadFileData
(
f
);
}
catch
(
Exception
e
)
{
System
.
out
.
println
(
"Exception executing: loading "
+
s
);
assertTrue
(
false
);
}
System
.
out
.
println
(
"executing: testing spec "
+
s
);
assertTrue
(
spec
!=
null
);
System
.
out
.
println
(
"executing: testing parsed "
+
s
);
boolean
parsed
=
tmts
.
makeTMLMapping
(
spec
,
RESOURCES_DIR
);
assertTrue
(
parsed
);
System
.
out
.
println
(
"executing: checking syntax "
+
s
);
// Checking syntax
TMLMapping
tmap
=
tmts
.
getTMLMapping
();
TMLSyntaxChecking
syntax
=
new
TMLSyntaxChecking
(
tmap
);
syntax
.
checkSyntax
();
assertTrue
(
syntax
.
hasErrors
()
==
0
);
// Generate SystemC code
System
.
out
.
println
(
"executing: sim code gen for "
+
s
);
final
IDiploSimulatorCodeGenerator
tml2systc
;
List
<
EBRDD
>
al
=
new
ArrayList
<
EBRDD
>();
List
<
TEPE
>
alTepe
=
new
ArrayList
<
TEPE
>();
tml2systc
=
DiploSimulatorFactory
.
INSTANCE
.
createCodeGenerator
(
tmap
,
al
,
alTepe
);
tml2systc
.
setModelName
(
s
);
String
error
=
tml2systc
.
generateSystemC
(
false
,
true
);
assertTrue
(
error
==
null
);
File
directory
=
new
File
(
SIM_DIR
);
if
(!
directory
.
exists
()){
directory
.
mkdirs
();
}
// Putting sim files
System
.
out
.
println
(
"SIM executing: sim lib code copying for "
+
s
);
ConfigurationTTool
.
SystemCCodeDirectory
=
getBaseResourcesDir
()
+
"../../../../simulators/c++2/"
;
boolean
simFiles
=
SpecConfigTTool
.
checkAndCreateSystemCDir
(
SIM_DIR
);
System
.
out
.
println
(
"SIM executing: sim lib code copying done with result "
+
simFiles
);
assertTrue
(
simFiles
);
System
.
out
.
println
(
"SIM Saving file in: "
+
SIM_DIR
);
tml2systc
.
saveFile
(
SIM_DIR
,
"appmodel"
);
// Compile it
System
.
out
.
println
(
"executing: compile"
);
Process
proc
;
BufferedReader
proc_in
;
String
str
;
boolean
mustRecompileAll
;
Penalties
penalty
=
new
Penalties
(
SIM_DIR
+
File
.
separator
+
"src_simulator"
);
int
changed
=
penalty
.
handlePenalties
(
false
);
if
(
changed
==
1
)
{
mustRecompileAll
=
true
;
}
else
{
mustRecompileAll
=
false
;
}
if
(
mustRecompileAll
)
{
System
.
out
.
println
(
"executing: "
+
"make -C "
+
SIM_DIR
+
" clean"
);
try
{
proc
=
Runtime
.
getRuntime
().
exec
(
"make -C "
+
SIM_DIR
+
" clean"
);
proc_in
=
new
BufferedReader
(
new
InputStreamReader
(
proc
.
getInputStream
()
)
);
while
(
(
str
=
proc_in
.
readLine
()
)
!=
null
)
{
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System
.
out
.
println
(
"executing: "
+
str
);
}
}
catch
(
Exception
e
)
{
// probably make is not installed
System
.
out
.
println
(
"FAILED: executing: "
+
"make -C "
+
SIM_DIR
+
" clean"
);
return
;
}
}
System
.
out
.
println
(
"executing: "
+
"make -C "
+
SIM_DIR
);
try
{
proc
=
Runtime
.
getRuntime
().
exec
(
"make -C "
+
SIM_DIR
+
""
);
proc_in
=
new
BufferedReader
(
new
InputStreamReader
(
proc
.
getInputStream
()
)
);
monitorError
(
proc
);
while
(
(
str
=
proc_in
.
readLine
()
)
!=
null
)
{
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System
.
out
.
println
(
"executing: "
+
str
);
}
}
catch
(
Exception
e
)
{
// Probably make is not installed
System
.
out
.
println
(
"FAILED: executing: "
+
"make -C "
+
SIM_DIR
);
return
;
}
System
.
out
.
println
(
"SUCCESS: executing: "
+
"make -C "
+
SIM_DIR
);
// Run the simulator
String
graphPath
=
SIM_DIR
+
"testgraph_"
+
s
;
try
{
String
[]
params
=
new
String
[
3
];
params
[
0
]
=
"./"
+
SIM_DIR
+
"run.x"
;
params
[
1
]
=
"-cmd"
;
params
[
2
]
=
"1 0; 1 7 100 100 "
+
graphPath
;
proc
=
Runtime
.
getRuntime
().
exec
(
params
);
//proc = Runtime.getRuntime().exec("./" + SIM_DIR + "run.x -explo -gname testgraph_" + s);
proc_in
=
new
BufferedReader
(
new
InputStreamReader
(
proc
.
getInputStream
()
)
);
monitorError
(
proc
);
while
(
(
str
=
proc_in
.
readLine
()
)
!=
null
)
{
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System
.
out
.
println
(
"executing: "
+
str
);
}
}
catch
(
Exception
e
)
{
// Probably make is not installed
System
.
out
.
println
(
"FAILED: executing simulation"
);
return
;
}
// Compare results with expected ones
// Must load the graph
File
graphFile
=
new
File
(
graphPath
+
".aut"
);
String
graphData
=
""
;
try
{
graphData
=
FileUtils
.
loadFileData
(
graphFile
);
}
catch
(
Exception
e
)
{
assertTrue
(
false
);
}
AUTGraph
graph
=
new
AUTGraph
();
graph
.
buildGraph
(
graphData
);
// States and transitions
System
.
out
.
println
(
"executing: nb states of "
+
s
+
" "
+
graph
.
getNbOfStates
());
assertTrue
(
NB_Of_DELAY_RW_STATES
[
i
]
==
graph
.
getNbOfStates
());
System
.
out
.
println
(
"executing: nb transitions of "
+
s
+
" "
+
graph
.
getNbOfTransitions
());
assertTrue
(
NB_Of_DELAY_RW_TRANSTIONS
[
i
]
==
graph
.
getNbOfTransitions
());
// Min and max cycles
int
minValue
=
graph
.
getMinValue
(
"allCPUsFPGAsTerminated"
);
System
.
out
.
println
(
"executing: minvalue of "
+
s
+
" "
+
minValue
);
assertTrue
(
MIN_DELAY_RW_CYCLES
[
i
]
==
minValue
);
int
maxValue
=
graph
.
getMaxValue
(
"allCPUsFPGAsTerminated"
);
System
.
out
.
println
(
"executing: maxvalue of "
+
s
+
" "
+
maxValue
);
assertTrue
(
MAX_DELAY_RW_CYCLES
[
i
]
==
maxValue
);
}
}
}
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