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Commit 5147f85c authored by Ludovic Apvrille's avatar Ludovic Apvrille
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Adding sources files for new sec. test

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ttool/src/test/resources/tmltranslator/test_diplo_security_models/symetric.tarchi 0 → 100644
+ 116
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View file @ 5147f85c
// Master clock frequency - in MHz
MASTERCLOCKFREQUENCY 200
NODE BRIDGE BridgeAlice
SET BridgeAlice bufferByteSize 4
SET BridgeAlice clockDivider 1
NODE BRIDGE BridgeBob
SET BridgeBob bufferByteSize 4
SET BridgeBob clockDivider 1
NODE MEMORY ExternalMemory
SET ExternalMemory byteDataSize 4
SET ExternalMemory clockDivider 1
NODE MEMORY MemoryAlice
SET MemoryAlice byteDataSize 4
SET MemoryAlice clockDivider 1
NODE MEMORY MemoryBob
SET MemoryBob byteDataSize 4
SET MemoryBob clockDivider 1
NODE BUS BusBob
SET BusBob byteDataSize 4
SET BusBob pipelineSize 1
SET BusBob arbitration 0
SET BusBob sliceTime 10000
SET BusBob burstSize 100
SET BusBob privacy private
SET BusBob clockDivider 1
NODE BUS BusAlice
SET BusAlice byteDataSize 4
SET BusAlice pipelineSize 1
SET BusAlice arbitration 0
SET BusAlice sliceTime 10000
SET BusAlice burstSize 100
SET BusAlice privacy private
SET BusAlice clockDivider 1
NODE BUS ExternalBus
SET ExternalBus byteDataSize 4
SET ExternalBus pipelineSize 1
SET ExternalBus arbitration 0
SET ExternalBus sliceTime 10000
SET ExternalBus burstSize 100
SET ExternalBus privacy public
SET ExternalBus clockDivider 1
NODE CPU CPUAlice
SET CPUAlice nbOfCores 1
SET CPUAlice byteDataSize 4
SET CPUAlice pipelineSize 5
SET CPUAlice goIdleTime 10
SET CPUAlice maxConsecutiveIdleCycles 10
SET CPUAlice taskSwitchingTime 20
SET CPUAlice branchingPredictionPenalty 2
SET CPUAlice cacheMiss 5
SET CPUAlice schedulingPolicy 0
SET CPUAlice sliceTime 10000
SET CPUAlice execiTime 1
SET CPUAlice execcTime 1
SET CPUAlice clockDivider 1
NODE CPU CPUBob
SET CPUBob nbOfCores 1
SET CPUBob byteDataSize 4
SET CPUBob pipelineSize 5
SET CPUBob goIdleTime 10
SET CPUBob maxConsecutiveIdleCycles 10
SET CPUBob taskSwitchingTime 20
SET CPUBob branchingPredictionPenalty 2
SET CPUBob cacheMiss 5
SET CPUBob schedulingPolicy 0
SET CPUBob sliceTime 10000
SET CPUBob execiTime 1
SET CPUBob execcTime 1
SET CPUBob clockDivider 1
NODE LINK link_CPUBob_to_BusBob
SET link_CPUBob_to_BusBob node CPUBob
SET link_CPUBob_to_BusBob bus BusBob
SET link_CPUBob_to_BusBob priority 0
NODE LINK link_CPUAlice_to_BusAlice
SET link_CPUAlice_to_BusAlice node CPUAlice
SET link_CPUAlice_to_BusAlice bus BusAlice
SET link_CPUAlice_to_BusAlice priority 0
NODE LINK link_BridgeBob_to_BusBob
SET link_BridgeBob_to_BusBob node BridgeBob
SET link_BridgeBob_to_BusBob bus BusBob
SET link_BridgeBob_to_BusBob priority 0
NODE LINK link_BridgeBob_to_ExternalBus
SET link_BridgeBob_to_ExternalBus node BridgeBob
SET link_BridgeBob_to_ExternalBus bus ExternalBus
SET link_BridgeBob_to_ExternalBus priority 0
NODE LINK link_BridgeAlice_to_ExternalBus
SET link_BridgeAlice_to_ExternalBus node BridgeAlice
SET link_BridgeAlice_to_ExternalBus bus ExternalBus
SET link_BridgeAlice_to_ExternalBus priority 0
NODE LINK link_BridgeAlice_to_BusAlice
SET link_BridgeAlice_to_BusAlice node BridgeAlice
SET link_BridgeAlice_to_BusAlice bus BusAlice
SET link_BridgeAlice_to_BusAlice priority 0
NODE LINK link_ExternalMemory_to_ExternalBus
SET link_ExternalMemory_to_ExternalBus node ExternalMemory
SET link_ExternalMemory_to_ExternalBus bus ExternalBus
SET link_ExternalMemory_to_ExternalBus priority 0
NODE LINK link_MemoryAlice_to_BusAlice
SET link_MemoryAlice_to_BusAlice node MemoryAlice
SET link_MemoryAlice_to_BusAlice bus BusAlice
SET link_MemoryAlice_to_BusAlice priority 0
NODE LINK link_MemoryBob_to_BusBob
SET link_MemoryBob_to_BusBob node MemoryBob
SET link_MemoryBob_to_BusBob bus BusBob
SET link_MemoryBob_to_BusBob priority 0
ttool/src/test/resources/tmltranslator/test_diplo_security_models/symetric.tmap 0 → 100644
+ 24
− 0
View file @ 5147f85c
TMLSPEC
#include "symetric.tml"
ENDTMLSPEC
TMLARCHI
#include "symetric.tarchi"
ENDTMLARCHI
TMLMAPPING
MAP CPUAlice SymmetricExchange__Alice
SET SymmetricExchange__Alice priority 0
MAP CPUBob SymmetricExchange__Bob
SET SymmetricExchange__Bob priority 0
MAP ExternalMemory SymmetricExchange__comm
SET SymmetricExchange__comm priority 0
MAP ExternalBus SymmetricExchange__comm
SET SymmetricExchange__comm priority 0
MAP BusAlice SymmetricExchange__comm
SET SymmetricExchange__comm priority 0
MAP BusBob SymmetricExchange__comm
SET SymmetricExchange__comm priority 0
MAPSEC MemoryAlice sym
MAPSEC MemoryBob sym
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/test_diplo_security_models/symetric.tml 0 → 100644
+ 34
− 0
View file @ 5147f85c
// TML Application - FORMAT 0.2
// Application: /Users/ludovicapvrille/TTool/modeling/SysMLSec/AliceAndBobHW.xml
// Generated: Mon May 15 19:50:10 CEST 2023
// PRAGMAS
// Channels
CHANNEL SymmetricExchange__comm NBRNBW 4 OUT SymmetricExchange__Alice IN SymmetricExchange__Bob
VCCHANNEL SymmetricExchange__comm 0
CONFCHANNEL SymmetricExchange__comm
AUTHCHANNEL SymmetricExchange__comm
// Events
// Requests
TASK SymmetricExchange__Alice
TASKOP
//Local variables
//Behavior
EXECC 100 sym SE 100 100 0 0 - -
WRITE SymmetricExchange__comm 1+0 sym
ENDTASK
TASK SymmetricExchange__Bob
TASKOP
//Local variables
//Behavior
READ SymmetricExchange__comm 1+0 sym
EXECC 100 sym SE 100 100 0 0 - -
ENDTASK
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