Commit 6eaf7fdb authored by Daniela Genius's avatar Daniela Genius
Browse files

adding MWMR coprocessors to simulation topcell

parent 4cd3e362
......@@ -49,9 +49,8 @@ package ddtranslatorSoclib;
import java.util.LinkedList;
import java.util.List;
import ui.tmldd.TMLArchiHWANode;//DG 23.08.
public class AvatarddSpecification{
private List<AvatarComponent> components;
private List<AvatarConnector> connectors;
private List<AvatarMappedObject> mappedObjects;
......@@ -195,7 +194,7 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
return crossbars;
}
/* public LinkedList<AvatarBridge> getAllBridge(){
/* public LinkedList<AvatarBridge> getAllBridge(){
LinkedList<AvatarBridge> bridges = new LinkedList<AvatarBridge>();
for (AvatarComponent bridge : components )
{
......@@ -212,16 +211,22 @@ There always is a RAM0, a TTY and an interconnect (Bus or VGMN or crossbar) othe
return getAllCrossbar().size();
}
public List<AvatarCoproMWMR> getAllCoproMWMR(){
/* DG 23.08. les hardware accelerators proviennent en fait de la specification DIPLODOCUS */
// copro= new AvatarCoproMWMR("test",0,0,0,10,8,8,1,1,1,1,false);
public List<AvatarCoproMWMR> getAllCoproMWMR(){
List<AvatarCoproMWMR> copros = new LinkedList<AvatarCoproMWMR>();
for (AvatarComponent copro : components )
{
if (copro instanceof AvatarCoproMWMR)
copros.add((AvatarCoproMWMR)copro);
if (copro instanceof AvatarCoproMWMR){
System.out.println("$$$$$$$Coproc added to specification!$$$$$$$");
copros.add((AvatarCoproMWMR)copro);
}
}
return copros;
}
}
public int getNbCPU(){
return (getAllCPU()).size();
......
......@@ -213,9 +213,22 @@ if(nb_clusters==0){
*/
//only non-clustered version
int i=0;
for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "), IntTab("+copro.getTgtid() + "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(), copro.getUseLLSC());"+ CR;
declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "), IntTab("+copro.getTgtid() + "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(), copro.getUseLLSC());"+ CR;
//one virtual component for each hardware accellerator
declaration += "caba::FifoVirtualCoprocessorWrapper(\"hwa"+i+"\",1,1,1,1);"+ CR;
//DG 23.08. a adapter
/*fifos_out,
fifos_out_width,
fifos_in,
fifos_in_width)*/
i++;
}
}
else {
......
......@@ -48,6 +48,8 @@
package ddtranslatorSoclib.toTopCell;
import ddtranslatorSoclib.*; //DG 23.08.
public class Header {
static private String header;
......@@ -89,7 +91,27 @@ int nb_clusters=5;
else{
header +="#include \"vci_vgmn.h\""+ CR;
}
int with_hw_accellerator = 1; //DG 23.08. a la main
if (with_hw_accellerator>0){
header +="#include \"vci_mwmr_controller.h\""+ CR;
}
//include statements for all coprocessors found
//The user must ensure that there is a SoCLib component corresponding to this coprocessor
// if (with_hw_accellerator>0){
//DG 23.08. actuellement il ne les trouve pas!
for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
// String name = HWAccelerator.getCoprocName();
// header +="#include \""+name+"\""+ CR;
//Per default for testing
// header +="#include \"input_coproc.h\""+ CR;
//header +="#include \"output_coproc.hh\""+ CR;
/* can be found in /users/outil/soc/soclib/soclib/module/internal_component/fifo* */
header +="#include \"fifo_virtual_coprocessor_wrapper.h\""+ CR;
}
// }
header+= "#include \"vci_block_device.h\"" + CR
+ "#include \"vci_simhelper.h\"" + CR + "#include \"vci_fd_access.h\"" + CR
+ "#include \"vci_ethernet.h\"" + CR
......
......@@ -51,6 +51,7 @@ package ddtranslatorSoclib.toTopCell;
import ddtranslatorSoclib.AvatarRAM;
import ddtranslatorSoclib.AvatarTTY;
import ddtranslatorSoclib.*;
public class MappingTable {
......@@ -167,6 +168,19 @@ public class MappingTable {
mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0xd1200000, 0x00000020, IntTab("+(l+3)+"), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"vci_locks\", 0xC0200000, 0x00000100, IntTab("+(l+4)+"), false));" + CR2;
int hwa_count=0;
int hwa_count2=0;
// if (with_hw_mwmr>0){
//les accellerateurs sont caches car apparaissent uniquement au niveau DIPLODOCUS
for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
// mapping += "maptab.add(Segment(\"mwmr"+HWAccelerator.getNo()+"\", MWMR_BASE , MWMR_SIZE , IntTab("+(m+hwa_count)+"), false));" + CR;
// mapping += "maptab.add(Segment(\"mwmr_ram"+HWAccelerator.getNo()+"\", MWMRd_BASE , MWMRd_SIZE , IntTab("+(m+hwa_count+1)+"), false));" + CR2;
mapping += "maptab.add(Segment(\"mwmr"+hwa_count+"\", MWMR_BASE , MWMR_SIZE , IntTab("+(m+hwa_count2)+"), false));" + CR;
mapping += "maptab.add(Segment(\"mwmr_ram"+hwa_count+"\", MWMRd_BASE , MWMRd_SIZE , IntTab("+(m+hwa_count2+1)+"), false));" + CR2;
hwa_count2+=2;
hwa_count++;
}
return mapping;
}
......@@ -262,7 +276,11 @@ mapping += "maptab.add(Segment(\"vci_rttimer\", 0x"+ Integer.toHexString(SEG_TIM
tty.setNo_target(nb_ram);
}
mapping += "maptab.add(Segment(\"vci_multi_tty"+tty.getIndex()+"\" , 0x"+Integer.toHexString(SEG_TTY_BASE + tty.getNo_cluster()* CLUSTER_SIZE)+", 0x00000010, IntTab("+tty.getNo_cluster()+","+(tty.getNo_target())+"), false));" + CR;
}
}
/* Add as manin mwmr controllers as there are hardware accelerators */
//int with_hw_accelerator = 0; //DG 23.08.
// }
}
return mapping;
}
......
......@@ -389,6 +389,27 @@ public class NetList {
}
}
}
//if (with_hw_accellerator>0){
int p=0;
//for testing: vci_synthetic_initiator.h and vci_synthetic_target.h
for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
/* netlist += "mwmr"+HWAccelerator.getNo()+".p_clk(signal_clk);" + CR;
netlist += "mwmr"+HWAccelerator.getNo()+".p_resetn(signal_resetn);" + CR;
netlist += "mwmr"+HWAccelerator.getNo()+".p_vci_initiator(signal_mwmr"+HWAccelerator.getNo()+"_initiator);" + CR;
netlist += " mwmr"+HWAccelerator.getNo()+".p_vci_target(signal_mwmr"+HWAccelerator.getNo()+"_target);" + CR;
netlist += " mwmr"+HWAccelerator.getNo()+".p_from_coproc["+HWAccelerator.getNo()+"](signal_fifo_to_ctrl);" + CR;
netlist += " mwmr"+HWAccelerator.getNo()+".p_to_coproc["+HWAccelerator.getNo()+"](signal_fifo_from_ctrl);" + CR;*/
netlist += "mwmr"+p+".p_clk(signal_clk);" + CR;
netlist += "mwmr"+p+".p_resetn(signal_resetn);" + CR;
netlist += "mwmr"+p+".p_vci_initiator(signal_mwmr"+p+"_initiator);" + CR;
netlist += " mwmr"+p+".p_vci_target(signal_mwmr"+p+"_target);" + CR;
netlist += " mwmr"+p+".p_from_coproc["+p+"](signal_fifo_to_ctrl);" + CR;
netlist += " mwmr"+p+".p_to_coproc["+p+"](signal_fifo_from_ctrl);" + CR;
}
// }
//generate trace file if marked trace option
......
......@@ -78,9 +78,11 @@ public class Platforminfo {
platforminfo+="Uses('caba:vci_vgmn'),"+CR;
}
//DG 23.08. added virtual coprocessor
platforminfo+="Uses('caba:vci_mwmr_stats'),"+CR
+"Uses('caba:vci_logger'),"+CR
+"Uses('caba:vci_local_crossbar'),"+CR
+"Uses('caba:vci_local_crossbar'),"+CR
+"Uses('caba:fifo_virtual_coprocessor_wrapper'),"+CR
+"Uses('common:elf_file_loader'),"+CR
+"Uses('common:plain_file_loader'),"+CR
+"Uses('caba:vci_xcache_wrapper', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:ppc405'),"+CR
......
......@@ -116,8 +116,26 @@ else{
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
i++;
}
signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
int p=0;
// if (with_hw_accellerator>0){ //DG 23.08.
for (AvatarCoproMWMR HWAccelerator : TopCellGenerator.avatardd.getAllCoproMWMR()) {
//les accellerateurs sont caches car apparaissent uniquement au niveau DIPLODOCUS
//signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr"+HWAccelerator.getNo()+"_target(\"signal_mwmr"+HWAccelerator.getNo()+"_target\""+CR;
//signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr"+HWAccelerator.getNo()+"_initiator(\"signal_mwmr"+HWAccelerator.getNo()+"_initiator\"" +CR;
//signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_to_ctrl"+HWAccelerator.getNo()+"(\"signal_fifo_to_ctrl"+HWAccelerator.getNo()+"\");"+CR;
//signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_from_ctrl"+HWAccelerator.getNo()+"(\"signal_fifo_from_ctrl"+HWAccelerator.getNo()+"\");"+CR;
signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr"+p+"_target(\"signal_mwmr"+p+"_target\""+CR;
signal = signal + " soclib::caba::VciSignals<vci_param> signal_mwmr"+p+"_initiator(\"signal_mwmr"+p+"_initiator\"" +CR;
signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_to_ctrl"+p+"(\"signal_fifo_to_ctrl"+p+"\");"+CR;
signal = signal + " soclib::caba::FifoSignals<uint32_t> signal_fifo_from_ctrl"+p+"(\"signal_fifo_from_ctrl"+p+"\");"+CR;
p++;
}
signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
//System.out.print("number of processors : " + TopCellGenerator.avatardd.getNbCPU()+"\n");
System.out.print("number of clusters : " + TopCellGenerator.avatardd.getNbClusters()+"\n");
......
......@@ -243,9 +243,12 @@ public class AvatarDeploymentPanelTranslator {
int nStatus = addCoproMWMRNode.getNStatus(); // nb of status registers
boolean useLLSC = addCoproMWMRNode.getUseLLSC(); // more efficient protocol. 0: not used. 1 or more -> used
// System.out.println("$$$$$$$$$$$Hardware Accelerator found$$$$$$$$$$$");
AvatarCoproMWMR acpMWMR;
acpMWMR = new AvatarCoproMWMR(timerName, srcid, srcid, tgtid, plaps, fifoToCoprocDepth, fifoFromCoprocDepth, nToCopro, nFromCopro, nConfig, nStatus, useLLSC);
avatarMap.put(dp, acpMWMR);
avatarComponents.add(acpMWMR);
} else if (dp instanceof ADDMemoryNode) {
......@@ -255,7 +258,7 @@ public class AvatarDeploymentPanelTranslator {
String name = addRamNode.getNodeName();
int index = addRamNode.getIndex();
int byteDataSize = addRamNode.getDataSize();
System.out.println("ADD RAM Data Size" + byteDataSize);
//int monitored = addRamNode.getMonitored();
System.out.println("ADD RAM monitored "+ addRamNode.getMonitored());
AvatarRAM avram = new AvatarRAM(name, index, byteDataSize, index, index, addRamNode.getMonitored());//DG 3.7.
......
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