Solving failed test: DiplodocusFPGAReconfigurationTests

ttool/src/test/java/tmltranslator/DiplodocusFPGAReconfigurationTests.java

@@ -27,11 +27,12 @@ public class DiplodocusFPGAReconfigurationTests extends AbstractTest {
 
     private static final String DIR_GEN = "test_diplo_simulator/";
     // test for reconfiguration of FPGA
-    private static final String [] MODELS_FPGA_RECONFIG = {"fpga_reconfig1", "fpga_reconfig2", "fpga_reconfig3", "fpga_reconfig4", "fpga_reconfig5", "fpga_reconfig6"};
-    private static final int [] NB_Of_FPGA_STATES = {20, 20, 20, 20, 20, 20};
-    private static final int [] NB_Of_FPGA_TRANSTIONS = {19, 19, 19, 19, 19, 19};
-    private static final int [] MIN_FPGA_CYCLES = {90, 83, 77, 70, 75, 76};
-    private static final int [] MAX_FPGA_CYCLES = {90, 83, 77, 70, 75, 76};
+    private static final String [] MODELS_FPGA_RECONFIG = {"fpga_reconfig1", "fpga_reconfig2", "fpga_reconfig3", "fpga_reconfig4",
+            "fpga_reconfig5", "fpga_reconfig6"};
+    private static final int [] NB_Of_FPGA_STATES =     {21, 21, 21, 21, 21, 21};
+    private static final int [] NB_Of_FPGA_TRANSTIONS = {20, 20, 20, 20, 20, 20};
+    private static final int [] MIN_FPGA_CYCLES =       {70, 63, 57, 56, 55, 56};
+    private static final int [] MAX_FPGA_CYCLES =       {70, 63, 57, 56, 55, 56};
 
     private static final String CPP_DIR = "../../../../simulators/c++2/";
     private String SIM_DIR;
@@ -79,6 +80,15 @@ public class DiplodocusFPGAReconfigurationTests extends AbstractTest {
 
             TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
             syntax.checkSyntax();
+
+            if (syntax.hasErrors() > 0) {
+                for (TMLError error: syntax.getErrors()) {
+                    System.out.println("Error: " + error.toString());
+                }
+
+            }
+
+
             assertTrue(syntax.hasErrors() == 0);
             // Generate SystemC code
             System.out.println("executing: sim code gen for " + s);
@@ -196,17 +206,19 @@ public class DiplodocusFPGAReconfigurationTests extends AbstractTest {
 
             // States and transitions
             System.out.println("executing: nb states of " + s + " " + graph.getNbOfStates());
-            assertTrue(NB_Of_FPGA_STATES[i] == graph.getNbOfStates());
             System.out.println("executing: nb transitions of " + s + " " + graph.getNbOfTransitions());
-            assertTrue(NB_Of_FPGA_TRANSTIONS[i] == graph.getNbOfTransitions());
 
             // Min and max cycles
             int minValue = graph.getMinValue("allCPUsFPGAsTerminated");
             System.out.println("executing: minvalue of " + s + " " + minValue);
-            assertTrue(MIN_FPGA_CYCLES[i] == minValue);
 
             int maxValue = graph.getMaxValue("allCPUsFPGAsTerminated");
             System.out.println("executing: maxvalue of " + s + " " + maxValue);
+
+            // Asserting graph values
+            assertTrue(MIN_FPGA_CYCLES[i] == minValue);
+            assertTrue(NB_Of_FPGA_STATES[i] == graph.getNbOfStates());
+            assertTrue(NB_Of_FPGA_TRANSTIONS[i] == graph.getNbOfTransitions());
             assertTrue(MAX_FPGA_CYCLES[i] == maxValue);
         }
     }

ttool/src/test/java/tmltranslator/MemoryLeakTest.java

@@ -35,10 +35,10 @@ public class MemoryLeakTest extends AbstractTest {
     final String DIR_GEN = "test_diplo_simulator/";
     final String [] MODELS_MEMORY_LEAK = {"fpga_reconfig5", "fpga_reconfig6"};
     private String SIM_DIR;
-    final int [] NB_OF_ML_STATES = {20, 20};
-    final int [] NB_OF_ML_TRANSTIONS = {19, 19};
-    final int [] MIN_ML_CYCLES = {75, 76};
-    final int [] MAX_ML_CYCLES = {75, 76};
+    final int [] NB_OF_ML_STATES = {21, 21};
+    final int [] NB_OF_ML_TRANSTIONS = {20, 20};
+    final int [] MIN_ML_CYCLES = {55, 56};
+    final int [] MAX_ML_CYCLES = {55, 56};
     static String CPP_DIR = "../../../../simulators/c++2/";
     static String valgrindVersionCmd = "valgrind --version";
     static String valgrindExecCmd = "valgrind --leak-check=full --log-file=";
@@ -86,7 +86,18 @@ public class MemoryLeakTest extends AbstractTest {
 
             TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
             syntax.checkSyntax();
+
+            if (syntax.hasErrors() > 0) {
+                for (TMLError error: syntax.getErrors()) {
+                    System.out.println("Error: " + error.toString());
+                }
+
+            }
+
             assertTrue(syntax.hasErrors() == 0);
+
+
+
             // Generate SystemC code
             System.out.println("executing: sim code gen for " + s);
             final IDiploSimulatorCodeGenerator tml2systc;

ttool/src/test/resources/tmltranslator/simulator/fpga_reconfig1.tmap

@@ -17,4 +17,5 @@ TMLMAPPING
     SET Application__Task2 priority 0
     MAP FPGA0 Application__Task5
     SET Application__Task5 priority 0
+    MAP Memory0 Application__ch
 ENDTMLMAPPING

ttool/src/test/resources/tmltranslator/simulator/fpga_reconfig2.tmap

@@ -17,4 +17,5 @@ TMLMAPPING
     SET Application__Task2 priority 0
     MAP FPGA0 Application__Task5
     SET Application__Task5 priority 0
+    MAP Memory0 Application__ch
 ENDTMLMAPPING

ttool/src/test/resources/tmltranslator/simulator/fpga_reconfig3.tmap

@@ -17,4 +17,5 @@ TMLMAPPING
     SET Application__Task2 priority 0
     MAP FPGA0 Application__Task5
     SET Application__Task5 priority 0
+    MAP Memory0 Application__ch
 ENDTMLMAPPING

ttool/src/test/resources/tmltranslator/simulator/fpga_reconfig4.tmap

@@ -17,4 +17,5 @@ TMLMAPPING
     SET Application__Task2 priority 0
     MAP FPGA0 Application__Task5
     SET Application__Task5 priority 0
+    MAP Memory0 Application__ch
 ENDTMLMAPPING

ttool/src/test/resources/tmltranslator/simulator/fpga_reconfig5.tmap

@@ -17,4 +17,5 @@ TMLMAPPING
     SET Application__Task2 priority 0
     MAP FPGA0 Application__Task5
     SET Application__Task5 priority 0
+    MAP Memory0 Application__ch
 ENDTMLMAPPING

ttool/src/test/resources/tmltranslator/simulator/fpga_reconfig6.tmap

@@ -17,4 +17,5 @@ TMLMAPPING
     SET Application__Task3 priority 0
     MAP FPGA0 Application__Task4
     SET Application__Task4 priority 0
+    MAP Memory0  Application__ch
 ENDTMLMAPPING