Commit 7ecf059d authored by Ludovic Apvrille's avatar Ludovic Apvrille

Revert "New test added. Changed folder configuration"

This reverts commit 4af9c8c5.
parent 2d1e5151
......@@ -1310,21 +1310,6 @@ ServerIF* Simulator::run(int iLen, char ** iArgs){
return 0;
}
bool Simulator::getDaemonTaskStatus(SimComponents* __simComp) {
int tempDaemon = 0;
if (!__simComp->getNonDaemonTaskList().empty()) {
for (TaskList::const_iterator i=__simComp->getNonDaemonTaskList().begin(); i != __simComp->getNonDaemonTaskList().end(); ++i) {
if((*i)->getState()==3){
tempDaemon ++;
}
}
}
if (tempDaemon < __simComp->getNonDaemonTaskList().size()) {
return false;
}
return true;
}
void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
std::cout<<"decodeCommand"<<std::endl;
//std::cout << "Not crashed. I: " << iCmd << std::endl;
......@@ -1370,7 +1355,15 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
std::cout << "Run to next breakpoint." << std::endl;
aGlobMsg << TAG_MSGo << "Run to next breakpoint" << TAG_MSGc << std::endl;
_simTerm=runToNextBreakpoint(oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
int tempDaemon = 0;
if (!_simComp->getNonDaemonTaskList().empty()) {
for (TaskList::const_iterator i=_simComp->getNonDaemonTaskList().begin(); i != _simComp->getNonDaemonTaskList().end(); ++i) {
if((*i)->getState()==3){
tempDaemon ++;
}
}
}
if (tempDaemon < _simComp->getNonDaemonTaskList().size()) {
_simTerm = false;
}
std::cout << "End Run to next breakpoint." << std::endl;
......@@ -1389,9 +1382,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunXTransactions(_simComp,aParam2);
aGlobMsg << TAG_MSGo << "Created listener run " << aParam2 << " transactions" << TAG_MSGc << std::endl;
_simTerm = runXTransactions(aParam2, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
std::cout << "Run x transactions." << std::endl;
break;
case 3: //Run up to command x
......@@ -1406,9 +1396,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunXCommands(_simComp,aParam2);
aGlobMsg << TAG_MSGo << "Created listener run " << aParam2 << " commands" << TAG_MSGc << std::endl;
_simTerm = runXCommands(aParam2, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
std::cout << "End Run x commands." << std::endl;
break;
case 5: //Run up to time x
......@@ -1417,9 +1404,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunXTimeUnits(_simComp,aParam2);
aGlobMsg << TAG_MSGo << "Created listener run to time " << aParam2 << TAG_MSGc << std::endl;
_simTerm = runTillTimeX(aParam2, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
std::cout << "End Run to time x." << std::endl;
break;
case 6: //Run for x time units
......@@ -1428,9 +1412,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunXTimeUnits(_simComp,aParam2+SchedulableDevice::getSimulatedTime());
aGlobMsg << TAG_MSGo << "Created listener run " << aParam2 << " time units" << TAG_MSGc << std::endl;
_simTerm = runXTimeUnits(aParam2, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
std::cout << "End Run for x time units." << std::endl;
break;
case 7: {//Explore Tree
......@@ -1515,9 +1496,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunTillTransOnDevice(_simComp, aSubject);
aGlobMsg << TAG_MSGo << "Created listener on Bus " << aStrParam << TAG_MSGc << std::endl;
_simTerm=runToBusTrans(aBus, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
}else{
aGlobMsg << TAG_MSGo << MSG_CMPNFOUND << TAG_MSGc << std::endl;
anErrorCode=2;
......@@ -1534,9 +1512,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunTillTransOnDevice(_simComp, aSubject);
aGlobMsg << TAG_MSGo << "Created listener on CPU " << aStrParam << TAG_MSGc << std::endl;
_simTerm=runToCPUTrans(aCPU, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
}else{
aGlobMsg << TAG_MSGo << MSG_CMPNFOUND << TAG_MSGc << std::endl;
anErrorCode=2;
......@@ -1552,9 +1527,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
if (aTask!=0){
aGlobMsg << TAG_MSGo << "Created listener on Task " << aStrParam << TAG_MSGc << std::endl;
_simTerm=runToTaskTrans(aTask, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
//_currCmdListener=new RunTillTransOnDevice(_simComp, aSubject);
}else{
......@@ -1573,9 +1545,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunTillTransOnDevice(_simComp, aSubject);
aGlobMsg << TAG_MSGo << "Created listener on Slave " << aStrParam << TAG_MSGc << std::endl;
_simTerm=runToSlaveTrans(aSlave, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
}else{
aGlobMsg << TAG_MSGo << MSG_CMPNFOUND << TAG_MSGc << std::endl;
anErrorCode=2;
......@@ -1592,9 +1561,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunTillTransOnDevice(_simComp, aSubject);
aGlobMsg << TAG_MSGo << "Created listener on Channel " << aStrParam << TAG_MSGc << std::endl;
_simTerm=runToChannelTrans(aChannel, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
}else{
aGlobMsg << TAG_MSGo << MSG_CMPNFOUND << TAG_MSGc << std::endl;
anErrorCode=2;
......@@ -1605,9 +1571,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
case 13:{//Run to next random choice command
std::cout << "Run to next random command." << std::endl;
_simTerm=runToNextRandomCommand(oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
std::cout << "End Run to next random choice command." << std::endl;
break;
}
......@@ -1642,9 +1605,6 @@ void Simulator::decodeCommand(std::string iCmd, std::ostream& iXmlOutStream){
//_currCmdListener=new RunTillTransOnDevice(_simComp, aSubject);
aGlobMsg << TAG_MSGo << "Created listener on FPGA " << aStrParam << TAG_MSGc << std::endl;
_simTerm=runToCPUTrans(aFPGA, oLastTrans);
if (!getDaemonTaskStatus(_simComp)) {
_simTerm = false;
}
}else{
aGlobMsg << TAG_MSGo << MSG_CMPNFOUND << TAG_MSGc << std::endl;
anErrorCode=2;
......
......@@ -267,8 +267,6 @@ public:
*/
void schedule2TXT(std::string& iTraceFileName) const;
bool getDaemonTaskStatus(SimComponents* __simComp);
void schedule2XML(std::ostringstream& glob,std::string& iTraceFileName) const;
/**
\param glob Stream on which the XML answer shall be send to
......
......@@ -86,39 +86,6 @@ public class CLIAvatarModelCheckerTest extends AbstractTest implements Interpret
System.out.println("info from interpreter:" + s);
}
@Test
public void testCoffeeMachine() {
String filePath = getBaseResourcesDir() + PATH_TO_TEST_FILE + "scriptmodelchecker";
String script;
File f = new File(filePath);
assertTrue(myutil.FileUtils.checkFileForOpen(f));
script = myutil.FileUtils.loadFileData(f);
assertTrue(script.length() > 0);
boolean show = false;
Interpreter interpret = new Interpreter(script, (InterpreterOutputInterface)this, show);
interpret.interpret();
// Must now load the graph
filePath = "rgmodelchecker.aut";
f = new File(filePath);
assertTrue(myutil.FileUtils.checkFileForOpen(f));
String data = myutil.FileUtils.loadFileData(f);
assertTrue(data.length() > 0);
AUTGraph graph = new AUTGraph();
graph.buildGraph(data);
graph.computeStates();
System.out.println("states=" + graph.getNbOfStates() + " transitions=" + graph.getNbOfTransitions());
assertTrue(graph.getNbOfStates() == 14);
assertTrue(graph.getNbOfTransitions() == 16);
}
}
package tmltranslator;
import java.io.BufferedReader;
import java.io.FileReader;
public class CommonMethods {
public static boolean compareTextFile (String filePath1, String filePath2) throws Exception {
BufferedReader reader1 = new BufferedReader(new FileReader(filePath1));
BufferedReader reader2 = new BufferedReader(new FileReader(filePath2));
String line1 = reader1.readLine();
String line2 = reader2.readLine();
boolean areEqual = true;
int lineNum = 1;
while (line1 != null || line2 != null) {
if (line1 == null || line2 == null) {
areEqual = false;
break;
} else if (!line1.equalsIgnoreCase(line2)) {
areEqual = false;
break;
}
line1 = reader1.readLine();
line2 = reader2.readLine();
lineNum++;
}
if (areEqual) {
System.out.println("Two files have same content.");
} else {
System.out.println("Two files have different content. They differ at line " + lineNum);
System.out.println("File1 has " + line1 + " and File2 has " + line2 + " at line " + lineNum);
}
reader1.close();
reader2.close();
return areEqual;
}
}
......@@ -45,14 +45,6 @@ public class DiplodocusSimulatorTest extends AbstractUITest {
final String MODELS_DAEMON_RTNB = "testDaemon";
final int [] DAEMON_RTNBP_1 = {16, 15, 205, 205};
final int [] DAEMON_RTNBP_2 = {28, 27, 408, 408};
// model for general simulation commands
final String MODELS_DAEMON_GENERAL_COMMANDS = "testDaemon";
final String GENERAL_RUN_TO_TIME_X = getBaseResourcesDir() + "tmltranslator/expected/expected_run_to_time_x.txt"; // 1 5
final String GENERAL_RUN_X_TIME_UNITS = getBaseResourcesDir() + "tmltranslator/expected/expected_run_x_time_units.txt"; // 1 6
final String GENERAL_RUN_X_TRANSACTIONS = getBaseResourcesDir() + "tmltranslator/expected/expected_run_x_transactions.txt"; // 1 2
final String GENERAL_RUN_X_COMMANDS = getBaseResourcesDir() + "tmltranslator/expected/expected_run_x_commands.txt"; // 1 4
private String SIM_DIR;
......@@ -593,184 +585,4 @@ public class DiplodocusSimulatorTest extends AbstractUITest {
System.out.println("executing: maxvalue of " + s + " " + maxValue);
assertTrue(DAEMON_RTNBP_2[3] == maxValue);
}
@Test
public void testGeneralSimulationCommands() throws Exception {
String s = MODELS_DAEMON_GENERAL_COMMANDS;
SIM_DIR = DIR_GEN + s + "_general_commands/";
System.out.println("executing: checking syntax " + s);
// select architecture tab
mainGUI.openProjectFromFile(new File(RESOURCES_DIR + s + ".xml"));
for(TURTLEPanel _tab : mainGUI.getTabs()) {
if(_tab instanceof TMLArchiPanel) {
for (TDiagramPanel tdp : _tab.getPanels()) {
if (tdp instanceof TMLArchiDiagramPanel) {
mainGUI.selectTab(tdp);
break;
}
}
break;
}
}
mainGUI.checkModelingSyntax(true);
TMLMapping tmap = mainGUI.gtm.getTMLMapping();
TMLSyntaxChecking syntax = new TMLSyntaxChecking(tmap);
syntax.checkSyntax();
assertTrue(syntax.hasErrors() == 0);
// Generate SystemC code
System.out.println("executing: sim code gen for " + s);
final IDiploSimulatorCodeGenerator tml2systc;
List<EBRDD> al = new ArrayList<EBRDD>();
List<TEPE> alTepe = new ArrayList<TEPE>();
tml2systc = DiploSimulatorFactory.INSTANCE.createCodeGenerator(tmap, al, alTepe);
tml2systc.setModelName(s);
String error = tml2systc.generateSystemC(false, true);
assertTrue(error == null);
File directory = new File(SIM_DIR);
if (!directory.exists()) {
directory.mkdirs();
}
// Putting sim files
System.out.println("SIM executing: sim lib code copying for " + s);
ConfigurationTTool.SystemCCodeDirectory = getBaseResourcesDir() + "../../../../simulators/c++2/";
boolean simFiles = SpecConfigTTool.checkAndCreateSystemCDir(SIM_DIR);
System.out.println("SIM executing: sim lib code copying done with result " + simFiles);
assertTrue(simFiles);
System.out.println("SIM Saving file in: " + SIM_DIR);
tml2systc.saveFile(SIM_DIR, "appmodel");
// Compile it
System.out.println("executing: compile");
Process proc;
BufferedReader proc_in;
String str;
boolean mustRecompileAll;
Penalties penalty = new Penalties(SIM_DIR + "src_simulator");
int changed = penalty.handlePenalties(false);
if (changed == 1) {
mustRecompileAll = true;
} else {
mustRecompileAll = false;
}
if (mustRecompileAll) {
System.out.println("executing: " + "make -C " + SIM_DIR + " clean");
try {
proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + " clean");
proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
while ((str = proc_in.readLine()) != null) {
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System.out.println("executing: " + str);
}
} catch (Exception e) {
// probably make is not installed
System.out.println("FAILED: executing: " + "make -C " + SIM_DIR + " clean");
return;
}
}
System.out.println("executing: " + "make -C " + SIM_DIR);
try {
proc = Runtime.getRuntime().exec("make -C " + SIM_DIR + "");
proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
monitorError(proc);
while ((str = proc_in.readLine()) != null) {
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System.out.println("executing: " + str);
}
} catch (Exception e) {
// Probably make is not installed
System.out.println("FAILED: executing: " + "make -C " + SIM_DIR);
return;
}
System.out.println("SUCCESS: executing: " + "make -C " + SIM_DIR);
// Run the simulator
String graphPath = SIM_DIR + "testgraph_" + s;
try {
// run to time x
String[] params = new String[3];
params[0] = "./" + SIM_DIR + "run.x";
params[1] = "-cmd";
params[2] = "11 4 21; 1 0; 1 5 3; 1 5 3; 7 2" + graphPath + "_run_to_time_x";
proc = Runtime.getRuntime().exec(params);
//proc = Runtime.getRuntime().exec("./" + SIM_DIR + "run.x -explo -gname testgraph_" + s);
proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
monitorError(proc);
while ((str = proc_in.readLine()) != null) {
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System.out.println("executing: " + str);
}
//run x time units
params = new String[3];
params[0] = "./" + SIM_DIR + "run.x";
params[1] = "-cmd";
params[2] = "11 4 21; 1 0; 1 6 3; 1 6 3; 7 2 " + graphPath + "_run_x_time_units";
proc = Runtime.getRuntime().exec(params);
//proc = Runtime.getRuntime().exec("./" + SIM_DIR + "run.x -explo -gname testgraph_" + s);
proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
monitorError(proc);
while ((str = proc_in.readLine()) != null) {
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System.out.println("executing second case: " + str);
}
//run x transactions
params = new String[3];
params[0] = "./" + SIM_DIR + "run.x";
params[1] = "-cmd";
params[2] = "11 4 21; 1 0; 1 2 3; 1 2 3; 1 2 3; 7 2 " + graphPath + "_run_x_transactions";
proc = Runtime.getRuntime().exec(params);
//proc = Runtime.getRuntime().exec("./" + SIM_DIR + "run.x -explo -gname testgraph_" + s);
proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
monitorError(proc);
while ((str = proc_in.readLine()) != null) {
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System.out.println("executing second case: " + str);
}
//run x commands
params = new String[3];
params[0] = "./" + SIM_DIR + "run.x";
params[1] = "-cmd";
params[2] = "11 4 21; 1 0; 1 4 3; 1 4 4; 7 2 " + graphPath + "_run_x_commands";
proc = Runtime.getRuntime().exec(params);
//proc = Runtime.getRuntime().exec("./" + SIM_DIR + "run.x -explo -gname testgraph_" + s);
proc_in = new BufferedReader(new InputStreamReader(proc.getInputStream()));
monitorError(proc);
while ((str = proc_in.readLine()) != null) {
// TraceManager.addDev( "Sending " + str + " from " + port + " to client..." );
System.out.println("executing second case: " + str);
}
} catch (Exception e) {
// Probably make is not installed
System.out.println("FAILED: executing simulation");
return;
}
assertTrue(CommonMethods.compareTextFile(graphPath + "_run_to_time_x.txt",GENERAL_RUN_TO_TIME_X));
assertTrue(CommonMethods.compareTextFile(graphPath + "_run_x_time_units.txt",GENERAL_RUN_X_TIME_UNITS));
assertTrue(CommonMethods.compareTextFile(graphPath + "_run_x_transactions.txt",GENERAL_RUN_X_TRANSACTIONS));
assertTrue(CommonMethods.compareTextFile(graphPath + "_run_x_commands.txt",GENERAL_RUN_X_COMMANDS));
}
}
\ No newline at end of file
========= Scheduling for device: CPU0_1 =========
FVWithRequest__Periodic: Send FVWithRequest__go__FVWithRequest__go(evtB) content:0 params: t:0 l:1 (vl:1) params: Ch: FVWithRequest__go__FVWithRequest__go
FVWithRequest__Sender: Wait FVWithRequest__go__FVWithRequest__go params: t:1 l:1 (vl:1) params: Ch: FVWithRequest__go__FVWithRequest__go
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:2 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:7 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
========= Scheduling for device: Bus0_0 =========
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:2 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:7 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
========= Scheduling for device: CPU0_1 =========
FVWithRequest__Periodic: Send FVWithRequest__go__FVWithRequest__go(evtB) content:0 params: t:0 l:1 (vl:1) params: Ch: FVWithRequest__go__FVWithRequest__go
FVWithRequest__Sender: Wait FVWithRequest__go__FVWithRequest__go params: t:1 l:1 (vl:1) params: Ch: FVWithRequest__go__FVWithRequest__go
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:2 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:7 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:12 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:17 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:22 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:27 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:32 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:37 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Periodic: IdleDL in FVWithRequest__Periodic len:1 progress:0 ID:24 t:42 l:1 (vl:1) params:
FVWithRequest__AnotherTask: Read 160,FVWithRequest__comm1__FVWithRequest__comm t:43 l:160 (vl:160) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
========= Scheduling for device: Bus0_0 =========
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:2 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:7 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:12 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:17 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:22 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:27 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:32 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:37 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
========= Scheduling for device: CPU0_1 =========
FVWithRequest__Periodic: Send FVWithRequest__go__FVWithRequest__go(evtB) content:0 params: t:0 l:1 (vl:1) params: Ch: FVWithRequest__go__FVWithRequest__go
FVWithRequest__Sender: Wait FVWithRequest__go__FVWithRequest__go params: t:1 l:1 (vl:1) params: Ch: FVWithRequest__go__FVWithRequest__go
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:2 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:7 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
========= Scheduling for device: Bus0_0 =========
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:2 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:7 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
========= Scheduling for device: CPU0_1 =========
FVWithRequest__Periodic: Send FVWithRequest__go__FVWithRequest__go(evtB) content:0 params: t:0 l:1 (vl:1) params: Ch: FVWithRequest__go__FVWithRequest__go
FVWithRequest__Sender: Wait FVWithRequest__go__FVWithRequest__go params: t:1 l:1 (vl:1) params: Ch: FVWithRequest__go__FVWithRequest__go
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:2 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:7 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:12 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:17 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:22 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:27 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:32 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:37 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Periodic: IdleDL in FVWithRequest__Periodic len:1 progress:0 ID:24 t:42 l:1 (vl:1) params:
========= Scheduling for device: Bus0_0 =========
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:2 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:7 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:12 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:17 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:22 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:27 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:32 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
FVWithRequest__Sender: Write 160,FVWithRequest__comm1__FVWithRequest__comm t:37 l:5 (vl:20) params: Ch: FVWithRequest__comm1__FVWithRequest__comm
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