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Commit 89bd05cb authored by Daniela Genius's avatar Daniela Genius
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rewritten mapping table generation

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src/ddtranslatorSoclib/toTopCell/MappingTable.java
+ 102
− 71
View file @ 89bd05cb
......@@ -60,19 +60,18 @@ public class MappingTable {
/* here we have a loop over the CHANNEL segments specified in the deployment diagram and we calculate their addresses in a loop; more refined methods may be proposed later */
int j=0;
//int k=0;
if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
//if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
/* Boot Ram segments 0,1,2 */
if(ram.getNo_ram() ==0){
ram.setNo_target(2);//in the following assign target number 2
mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, 0x00100000, IntTab("+(ram.getNo_target())+"), false));" + CR;
mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, 0x00100000, IntTab("+(ram.getNo_target())+"), true));" + CR;
mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0200000, 0x00100000, IntTab("+(ram.getNo_target())+"), false));" + CR;
}
else{
ram.setNo_target(7+j);
mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, 0x00100000, IntTab("+(ram.getNo_target())+"), false));" + CR;
mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, 0x00100000, IntTab("+(ram.getNo_target())+"), true));" + CR;
mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0200000, 0x00100000, IntTab("+(ram.getNo_target())+"), false));" + CR;
j++;
}
......@@ -90,96 +89,128 @@ public class MappingTable {
m++;
l=tty.getNo_target();
}
}
else{
/* clustered version */
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0000000, 0x00100000, IntTab("+ram.getNo_cluster()+","+(ram.getNo_target()+2)+"), false));" + CR;
mapping += "maptab.add(Segment(\"uram" + ram.getNo_ram() + "\", 0x" +(ram.getNo_ram()+1)+ "0200000, 0x00100000, IntTab("+ram.getNo_cluster()+","+(ram.getNo_target()+2)+"), false));" + CR;
}
int m=0;
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
/* we calculate the target number of one or several (multi-) ttys which come after the j rams and the 7 compulsory targets */
tty.setNo_target(7+j);
/* we use a simple formula for calculating the TTY address in case of multiple (multi-) ttys */
/* only one tty per cluster currently */
// mapping += "maptab.add(Segment(\"vci_multi_tty\" , 0xd"+tty.getNo_tty()+"200000, 0x00000010, IntTab("+m+","+tty.getNo_target() +"), false));" + CR;
mapping += "maptab.add(Segment(\"vci_multi_tty"+m+"\", 0xe"+(m+1)+"200000, 0x00000010, IntTab("+m+","+tty.getNo_target() +"), false));" + CR;
j++;
m++;
l=tty.getNo_target();
}
}
// }
mapping = mapping + "maptab.add(Segment(\"vci_fd_access\", 0xd4200000, 0x00000100, IntTab("+(l+1)+"), false));" + CR;
mapping = mapping + "maptab.add(Segment(\"vci_ethernet\", 0xd5000000, 0x00000020, IntTab("+(l+2)+"), false));" + CR;
mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0xd1200000, 0x00000020, IntTab("+(l+3)+"), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"vci_locks\", 0xC0200000, 0x00000100, IntTab("+(l+4)+"), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"mwmr_ram\", 0xA0200000, 0x00001000, IntTab("+(l+5)+"), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"mwmrd_ram\", 0xB0200000, 0x00003000, IntTab("+(l+6)+"), false));" + CR2;
// mapping = mapping + "maptab.add(Segment(\"mwmr_ram\", 0xA0200000, 0x00001000, IntTab("+(l+5)+"), false));" + CR2;
//mapping = mapping + "maptab.add(Segment(\"mwmrd_ram\", 0xB0200000, 0x00003000, IntTab("+(l+6)+"), false));" + CR2;
//DG 29.08.
// mapping = mapping + "maptab.add(Segment(\"cram\", 0xA0200000, 0x00001000, IntTab("+(l+5)+"), true));" + CR2;
//mapping = mapping + "maptab.add(Segment(\"uram\", 0xB0200000, 0x00003000, IntTab("+(l+6)+"), false));" + CR2;
return mapping;
}
///////////////////////////////////////////////////////////////////////////////////////////////////
// Mapping Table //
// There are 4 replicated segments in each cluster, and 8 single (not replicated) segments. //
// - Peripheral single segments (rom, ramdac, tg) are mapped in the cluster_rom and cluster_io. //
// - RAM single segments are mapped in each cluster at the first addresse of the cluster. //
// - Peripherals replicated segments (timer, icu, dma) are replicated in each cluster. //
///////////////////////////////////////////////////////////////////////////////////////////////////
/* MappingTable maptab(32, IntTab(8,4), IntTab(8,4), 0xFFFF0000);
maptab.add(Segment("seg_ie" , SEG_IE_BASE , SEG_IE_SIZE , IntTab(cluster_io , TGTID_IE), false));
maptab.add(Segment("seg_oe", SEG_OE_BASE, SEG_OE_SIZE, IntTab(cluster_io , TGTID_OE), false));
maptab.add(Segment("seg_tty" , SEG_TTY_BASE , SEG_TTY_SIZE , IntTab(cluster_io , TGTID_TTY), false));
maptab.add(Segment("seg_reset" , SEG_RESET_BASE , SEG_RESET_SIZE , IntTab(cluster_rom, tgtid_rom), true));
for (size_t c = 0; c < nc; c++) {
uint32_t ram_base = SEG_RAM_BASE + c * CLUSTER_SIZE;
uint32_t ram_size = SEG_RAM_SIZE;
std::ostringstream seg_ram_name;
seg_ram_name << "seg_ram_" << c;
maptab.add(Segment(seg_ram_name.str(), ram_base, ram_size, IntTab(c, TGTID_RAM), true));
uint32_t timer_base = SEG_TIM_BASE + c * CLUSTER_SIZE;
uint32_t timer_size = SEG_TIM_SIZE;
std::ostringstream seg_timer_name;
seg_timer_name << "seg_timer_" << c;
maptab.add(Segment(seg_timer_name.str(), timer_base, timer_size, IntTab(c, TGTID_TIM), true));
uint32_t icu_base = SEG_ICU_BASE + c * CLUSTER_SIZE;
uint32_t icu_size = SEG_ICU_SIZE;
std::ostringstream seg_icu_name;
seg_icu_name << "seg_icu_" << c;
maptab.add(Segment(seg_icu_name.str(), icu_base, icu_size, IntTab(c, TGTID_ICU), false)); */
else{
//clustered version
mapping = CR2 + "//-----------------------mapping table------------------------" + CR2;
mapping = mapping + "// ppc segments" + CR2;
/* clustered version */
mapping = mapping + "maptab.add(Segment(\"resetppc\", 0xffffff80, 0x0080, IntTab(0,1), true));" + CR;
mapping = CR2 + "maptab.add(Segment(\"resetppc\", 0xffffff80, 0x0080, IntTab(0,1), true));" + CR;
mapping = mapping + "maptab.add(Segment(\"resetnios\", 0x00802000, 0x1000, IntTab(0,1), true));" + CR;
mapping = mapping + "maptab.add(Segment(\"resetzero\", 0x00000000, 0x1000, IntTab(0,1), true));" + CR;
mapping = mapping + "maptab.add(Segment(\"resetmips\", 0xbfc00000, 0x1000, IntTab(0,1), true));" + CR;
mapping += CR2 + "// RAM shared segments" + CR2;
mapping += CR2 + "// RAM shared segments on cluster 0" + CR2;
mapping += "maptab.add(Segment(\"text\", 0x60000000, 0x00100000, IntTab(0,0), true));" + CR;
mapping += "maptab.add(Segment(\"rodata\", 0x80000000, 0x01000000, IntTab(0,1), true));" + CR;
mapping += "maptab.add(Segment(\"data\", 0x7f000000, 0x01000000, IntTab(0,2), false)); " + CR2;
mapping = mapping + "maptab.add(Segment(\"simhelper\", 0xd3200000, 0x00000100, IntTab(0,3), false));" + CR;
mapping = mapping + " maptab.add(Segment(\"vci_xicu\", 0xd2200000, 0x00001000, IntTab(0,4), false));" + CR;
mapping = mapping + "maptab.add(Segment(\"vci_rttimer\", 0xd6000000, 0x00000100, IntTab(0,5), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"simhelper\", 0xd3200000, 0x00000100, IntTab(0,3), false));" + CR;
mapping = mapping + "maptab.add(Segment(\"vci_fdt_rom\", 0xe0000000, 0x00001000, IntTab(0,6), false));" + CR2;
//fixed adresses also for the following hidden components, all in cluster 0 exclusively
mapping = mapping + "maptab.add(Segment(\"vci_fd_access\", 0xd4200000, 0x00000100, IntTab(0,7), false));" + CR;
mapping = mapping + "maptab.add(Segment(\"vci_ethernet\", 0xd5000000, 0x00000020, IntTab(0,8), false));" + CR;
mapping = mapping + "maptab.add(Segment(\"vci_block_device\", 0xd1200000, 0x00000020, IntTab(0,9), false));" + CR2;
int j=0; int c;
for (AvatarChannel channel : TopCellGenerator.avatardd.getAllMappedChannels()) {
//we need to know on which cluster the channel is mapped
mapping += "maptab.add(Segment(\"channel" + j+ "\", 0x" + channel.getNo_cluster() + "f000000, 0x00100000, IntTab("+channel.getNo_cluster()+","+channel.getRAMNo()+"), false));" + CR;
j++;
}
// DG 24.08. mettre a jour pour eviter le chevauchement des segments
for(c=0;c<nb_clusters;c++){
// mapping = mapping + "maptab.add(Segment(\"vci_locks"+c+"\", 0xC0200000, 0x00000100, IntTab("+c+",3), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"vci_locks"+c+"\", 0xC"+c+"200000, 0x00000100, IntTab("+c+",3), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"mwmr_ram"+c+"\", 0xA"+c+"200000, 0x00001000, IntTab("+c+",1), false));" + CR2;
mapping = mapping + "maptab.add(Segment(\"mwmrd_ram"+c+"\", 0xB"+c+"200000, 0x00003000, IntTab("+c+",2), false));" + CR2;
}
//one RAM and TTY per cluster independently of user
//now treat ram and tty
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
c=ram.getIndex();
ram.setNo_target(4);
mapping += "maptab.add(Segment(\"vci_multi_ram"+ram.getIndex()+"\" , 0xd"+ram.getIndex()+"0200000, 0x00010000, IntTab("+ram.getIndex()+",5), false));" + CR;
}
// uint32_t ram_base = SEG_RAM_BASE + c * CLUSTER_SIZE;
// soft/hard_config.h:#define CLUSTER_SIZE 0x40000000
int SEG_RAM_BASE = 0x00000000;
int SEG_RAM_SIZE = 0x00100000;
int SEG_ICU_BASE = 0x00100000;
int SEG_ICU_SIZE = 0x00000014;
int NB_TIMERS = 1;
int SEG_TIM_BASE = 0x00300000;
int SEG_TIM_SIZE = (NB_TIMERS * 16 );
//one tty per cluster
int i=0;
int CLUSTER_SIZE = 0x40000000;
//uint32_t ram_base = SEG_RAM_BASE + c * CLUSTER_SIZE;
// currently no DMA
//In cluster 0
int cluster = 0;
mapping += "maptab.add(Segment(\"cram0\", 0x"+ (SEG_RAM_BASE + cluster * CLUSTER_SIZE)+", 0x"+SEG_RAM_SIZE+", IntTab(0,10), true));" + CR;
mapping += "maptab.add(Segment(\"uram0\", 0x"+ (SEG_RAM_BASE+0x00200000)+", 0x"+SEG_RAM_SIZE+", IntTab(0,11), true));" + CR;
mapping += "maptab.add(Segment(\"icu0" + cluster + "\", 0x"+ (SEG_ICU_BASE)+", 0x"+SEG_ICU_SIZE+", IntTab(0,12);" + CR;
mapping += "maptab.add(Segment(\"timer0" + cluster + "\", 0x"+ (SEG_TIM_BASE)+", 0x"+SEG_TIM_SIZE+", IntTab(0,13), true));" + CR;
// in all other clusters
for(cluster=1;cluster<nb_clusters; cluster++){
mapping += "maptab.add(Segment(\"cram" +cluster+ "\", 0x"+ (SEG_RAM_BASE + cluster * CLUSTER_SIZE)+", 0x"+SEG_RAM_SIZE+", IntTab("+cluster+","+0+"), true));" + CR;
mapping += "maptab.add(Segment(\"uram" + cluster + "\", 0x"+ (SEG_RAM_BASE + cluster * CLUSTER_SIZE+0x00200000)+", 0x"+SEG_RAM_SIZE+", IntTab("+cluster+","+1+"), true));" + CR;
mapping += "maptab.add(Segment(\"icu" + cluster + "\", 0x"+ (SEG_ICU_BASE + cluster * CLUSTER_SIZE+0x00200000)+", 0x"+SEG_ICU_SIZE+", IntTab("+cluster +","+2+"), true));" + CR;
mapping += "maptab.add(Segment(\"timer" + cluster + "\", 0x"+ (SEG_TIM_BASE + cluster * CLUSTER_SIZE+0x00200000)+", 0x"+SEG_TIM_SIZE+", IntTab("+cluster +","+3+"), true));" + CR;
//later we will add DMA etc.
}
//several RAM or TTY per cluster
/* for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
mapping += "maptab.add(Segment(\"cram" + ram.getNo_ram() + "\", 0x"++", 0x"++", IntTab("+ram.getNo_cluster()+","+(ram.getNo_target())+"), true));" + CR;
}
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()) {
c=tty.getIndex();
tty.setNo_target(5);
// mapping += "maptab.add(Segment(\"vci_multi_tty"+tty.getIndex()+"\" , 0xd"+tty.getIndex()+"0200000, 0x00000010, IntTab("+tty.getIndex()+",5), false));" + CR;
mapping += "maptab.add(Segment(\"vci_multi_tty"+i+"\" , 0xd"+tty.getIndex()+"0200000, 0x00000010, IntTab("+tty.getIndex()+",5), false));" + CR;
i++;
}
c=tty.getIndex();
tty.setNo_target(10);
mapping += "maptab.add(Segment(\"vci_multi_tty"+tty.getIndex()+"\" , 0x"+(tty.getIndex()+1)+"e200000, 0x00000010, IntTab("+tty.getIndex()+","+(10+i)+"), false));" + CR;
}
}*/
}
return mapping;
}
}
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