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Commit 970be8cd authored by Ludovic Apvrille's avatar Ludovic Apvrille
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Merge branch 'master' of gitlab.enst.fr:mbe-tools/TTool

parents 75bc2746 58193ded
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build.txt
+ 1
− 1
View file @ 970be8cd
12990
\ No newline at end of file
12991
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modeling/DIPLODOCUS/CloneCompositeComponentTest.xml
+ 543
− 450
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This diff is collapsed.
src/main/java/ui/util/DefaultText.java
+ 2
− 2
View file @ 970be8cd
......@@ -50,8 +50,8 @@ package ui.util;
*/
public class DefaultText {
public static String BUILD = "12989";
public static String DATE = "2019/03/24 03:02:14 CET";
public static String BUILD = "12990";
public static String DATE = "2019/03/25 03:02:17 CET";
public static StringBuffer sbAbout = makeAbout();
......
ttool/src/test/java/ui/TDiagramPanelCloneArchitectureTest.java 0 → 100644
+ 109
− 0
View file @ 970be8cd
package ui;
import myutil.TraceManager;
import org.junit.*;
import tmltranslator.compareTMLTest.CompareTML;
import ui.tmldd.TMLArchiDiagramPanel;
import java.io.*;
import static org.junit.Assert.*;
/*
* #issue 186
* author : Minh Hiep
*/
public class TDiagramPanelCloneArchitectureTest extends AbstractUITest {
static TDiagramPanel architecture;
static TGComponent cpu1;
static TGComponent mapChannel;
final static String EXPECTED_FILE1 = getBaseResourcesDir() + "tmltranslator/expected/expected_spec1.tmap";
final static String EXPECTED_FILE2 = getBaseResourcesDir() + "tmltranslator/expected/expected_spec2.tarchi";
@BeforeClass
public static void setUpBeforeClass() throws Exception {
RESOURCES_DIR = getBaseResourcesDir() + "/ui/diagram2tml/input/CloneCompositeComponentTest.xml";
}
public TDiagramPanelCloneArchitectureTest() {
super();
mainGUI.openProjectFromFile(new File(RESOURCES_DIR));
}
@Before
public void setUp() {
architecture = null;
for(TURTLEPanel _tab : mainGUI.getTabs()) {
if(_tab instanceof TMLArchiPanel) {
for (TDiagramPanel tdp : _tab.getPanels()) {
if (tdp instanceof TMLArchiDiagramPanel) {
architecture = tdp;
mainGUI.selectTab(architecture);
break;
}
}
break;
}
}
if (architecture != null) {
//TraceManager.addDev("architecture tab is non null");
for (TGComponent tgc : architecture.getAllComponentList()) {
if (tgc.getValue().equals("Application::PrimitiveComp1")) {
mapChannel = tgc;
}
if (tgc.getName().equals("CPU1")) {
cpu1 = tgc;
}
}
}
}
@Test
public void testCloneMapInArchitecture() throws Exception {
CompareTML compTML = new CompareTML();
TGComponent mapTaskClone = null;
architecture.cloneComponent(mapChannel);
architecture.removeComponent(mapChannel);
for (TGComponent tgc : architecture.getComponentList()) {
if (tgc.getValue().equals("Application::PrimitiveComp1")) {
mapTaskClone = tgc;
}
}
if (mapTaskClone != null) {
//TraceManager.addDev("mapTaskClone is non null");
architecture.attach(mapTaskClone);
}
mainGUI.checkModelingSyntax(true);
mainGUI.generateTMLTxt();
File f1 = new File(EXPECTED_FILE1);
File f2 = new File("spec.tmap"); // Generated file after executing "TML generation"
assertTrue(compTML.compareTML(f1,f2));
}
@Test
public void testCloneNodeInArchitecture() throws Exception {
CompareTML compTML = new CompareTML();
architecture.cloneComponent(cpu1);
for (TGComponent tgc : architecture.getComponentList()) {
if (tgc.getName().equals("CPU1")) {
tgc.setName("CPU2");
break;
}
}
mainGUI.checkModelingSyntax(true);
mainGUI.generateTMLTxt();
File f1 = new File(EXPECTED_FILE2);
File f2 = new File("spec.tarchi"); // Generated file after executing "TML generation"
assertTrue(compTML.compareTML(f1,f2));
}
}
\ No newline at end of file
ttool/src/test/java/ui/TDiagramPanelCloneTest.java
+ 35
− 17
View file @ 970be8cd
package ui;
import myutil.TraceManager;
import org.junit.*;
import tmltranslator.compareTMLTest.CompareTML;
import ui.tmlcompd.TMLCCompositeComponent;
import ui.tmlcompd.TMLComponentTaskDiagramPanel;
import java.io.*;
import static org.junit.Assert.*;
/*
* #issue 82
* #issue 82 + 186
* author : Minh Hiep
*/
public class TDiagramPanelCloneTest extends AbstractUITest {
......@@ -18,9 +19,12 @@ public class TDiagramPanelCloneTest extends AbstractUITest {
static TGComponent tgComponent1;
static TGComponent tgComponent2;
static TGComponent tgComponent3;
static TGComponent tgComponent4;
final static String EXPECTED_FILE1 = getBaseResourcesDir() + "tmltranslator/expected/expected_spec1.tml";
final static String EXPECTED_FILE2 = getBaseResourcesDir() + "tmltranslator/expected/expected_spec2.tml";
final static String EXPECTED_FILE3 = getBaseResourcesDir() + "tmltranslator/expected/expected_spec3.tml";
final static String EXPECTED_FILE4 = getBaseResourcesDir() + "tmltranslator/expected/expected_spec4.tml";
@BeforeClass
......@@ -41,7 +45,7 @@ public class TDiagramPanelCloneTest extends AbstractUITest {
for (TDiagramPanel tdp : _tab.getPanels()) {
if (tdp instanceof TMLComponentTaskDiagramPanel) {
diagramPanel = tdp;
mainGUI.selectTab(tdp);
mainGUI.selectTab(diagramPanel);
break;
}
}
......@@ -49,26 +53,32 @@ public class TDiagramPanelCloneTest extends AbstractUITest {
}
}
for (TGComponent tgc : diagramPanel.getAllComponentList()) {
if (tgc.getValue().equals("CompositeComp1")) {
tgComponent1 = tgc;
}
if (diagramPanel != null) {
//TraceManager.addDev("diagram pannel is non null !!!");
for (TGComponent tgc : diagramPanel.getAllComponentList()) {
if (tgc.getValue().equals("CompositeComp1")) {
tgComponent1 = tgc;
}
if (tgc.getValue().equals("CompositeComp2")) {
tgComponent2 = tgc;
}
if (tgc.getValue().equals("CompositeComp2")) {
tgComponent2 = tgc;
}
if (tgc.getValue().equals("PrimitiveComp5")) {
tgComponent3 = tgc;
}
if (tgc.getValue().equals("PrimitiveComp5")) {
tgComponent3 = tgc;
if (tgc.getValue().equals("PrimitiveComp6")) {
tgComponent4 = tgc;
}
}
}
}
}
@Test
public void testCloneCompositeComponentWithNullFather() throws Exception{
CompareTML compTML = new CompareTML();
diagramPanel.cloneComponent(tgComponent1);
// mainGUI.modelChecking();
mainGUI.checkModelingSyntax(true);
mainGUI.generateTMLTxt();
File f1 = new File(EXPECTED_FILE1);
......@@ -80,7 +90,6 @@ public class TDiagramPanelCloneTest extends AbstractUITest {
public void testCloneCompositeComponentWithNonNullFather() throws Exception {
CompareTML compTML = new CompareTML();
diagramPanel.cloneComponent(tgComponent2);
// mainGUI.modelChecking();
mainGUI.checkModelingSyntax(true);
mainGUI.generateTMLTxt();
File f1 = new File(EXPECTED_FILE2);
......@@ -89,7 +98,7 @@ public class TDiagramPanelCloneTest extends AbstractUITest {
}
@Test
public void testClonePrimitiveComponent() throws Exception {
public void testClonePrimitiveComponentWithNonNullFather() throws Exception {
CompareTML compTML = new CompareTML();
diagramPanel.cloneComponent(tgComponent3);
// mainGUI.modelChecking();
......@@ -101,6 +110,15 @@ public class TDiagramPanelCloneTest extends AbstractUITest {
}
@Test
public void testClonePrimitiveComponentWithNullFather() throws Exception {
CompareTML compTML = new CompareTML();
diagramPanel.cloneComponent(tgComponent4);
mainGUI.checkModelingSyntax(true);
mainGUI.generateTMLTxt();
File f1 = new File(EXPECTED_FILE4);
File f2 = new File("spec.tml"); // Generated file after executing "TML generation"
assertTrue(compTML.compareTML(f1,f2));
}
}
\ No newline at end of file
ttool/src/test/resources/tmltranslator/expected/expected_spec1.tmap 0 → 100644
+ 22
− 0
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TMLSPEC
#include "spec.tml"
ENDTMLSPEC
TMLARCHI
#include "spec.tarchi"
ENDTMLARCHI
TMLMAPPING
MAP CPU0 Application__PrimitiveComp1
SET Application__PrimitiveComp1 priority 0
MAP CPU0 Application__PrimitiveComp6
SET Application__PrimitiveComp6 priority 0
MAP CPU0 Application__PrimitiveComp5
SET Application__PrimitiveComp5 priority 0
MAP CPU0 Application__PrimitiveComp4
SET Application__PrimitiveComp4 priority 0
MAP CPU0 Application__PrimitiveComp3
SET Application__PrimitiveComp3 priority 0
MAP CPU0 Application__PrimitiveComp2
SET Application__PrimitiveComp2 priority 0
ENDTMLMAPPING
\ No newline at end of file
ttool/src/test/resources/tmltranslator/expected/expected_spec1.tml
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// TML Application - FORMAT 0.1
// Application: /home/pham/Documents/TToolHelp/TTool/modeling/DIPLODOCUS/CloneCompositeComponentTest.xml
// Generated: Wed Mar 20 17:19:43 CET 2019
// Generated: Thu Mar 21 16:19:07 CET 2019
// Channels
CHANNEL DIPLODOCUS_C_Design__channel BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp1 IN DIPLODOCUS_C_Design__PrimitiveComp2
CHANNEL DIPLODOCUS_C_Design__channel2 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp3 IN DIPLODOCUS_C_Design__PrimitiveComp4
CHANNEL DIPLODOCUS_C_Design__channel2_0 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp3_0 IN DIPLODOCUS_C_Design__PrimitiveComp4_0
CHANNEL DIPLODOCUS_C_Design__channel3 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp5 IN DIPLODOCUS_C_Design__PrimitiveComp5
CHANNEL DIPLODOCUS_C_Design__channel3_0 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp5_0 IN DIPLODOCUS_C_Design__PrimitiveComp5_0
CHANNEL DIPLODOCUS_C_Design__channel_0 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp1_0 IN DIPLODOCUS_C_Design__PrimitiveComp2_0
CHANNEL Application__channel BRBW 4 8 OUT Application__PrimitiveComp1 IN Application__PrimitiveComp2
CHANNEL Application__channel2 BRBW 4 8 OUT Application__PrimitiveComp3 IN Application__PrimitiveComp4
CHANNEL Application__channel2_0 BRBW 4 8 OUT Application__PrimitiveComp3_0 IN Application__PrimitiveComp4_0
CHANNEL Application__channel3 BRBW 4 8 OUT Application__PrimitiveComp5 IN Application__PrimitiveComp5
CHANNEL Application__channel3_0 BRBW 4 8 OUT Application__PrimitiveComp5_0 IN Application__PrimitiveComp5_0
CHANNEL Application__channel4 BRBW 4 8 OUT Application__PrimitiveComp6 IN Application__PrimitiveComp6
CHANNEL Application__channel_0 BRBW 4 8 OUT Application__PrimitiveComp1_0 IN Application__PrimitiveComp2_0
// Events
EVENT DIPLODOCUS_C_Design__event_0__DIPLODOCUS_C_Design__event_0() NIB 8 DIPLODOCUS_C_Design__PrimitiveComp1_0 DIPLODOCUS_C_Design__PrimitiveComp2_0
EVENT DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event() NIB 8 DIPLODOCUS_C_Design__PrimitiveComp1 DIPLODOCUS_C_Design__PrimitiveComp2
EVENT Application__event_0__Application__event_0() NIB 8 Application__PrimitiveComp1_0 Application__PrimitiveComp2_0
EVENT Application__event__Application__event() NIB 8 Application__PrimitiveComp1 Application__PrimitiveComp2
// Requests
TASK DIPLODOCUS_C_Design__PrimitiveComp1
TASK Application__PrimitiveComp1
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
NOTIFY DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event
NOTIFY Application__event__Application__event
ENDCASERAND
CASERAND 50
WRITE DIPLODOCUS_C_Design__channel 1
WRITE Application__channel 1
ENDCASERAND
ENDRAND
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp1_0
TASK Application__PrimitiveComp1_0
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
NOTIFY DIPLODOCUS_C_Design__event_0__DIPLODOCUS_C_Design__event_0
NOTIFY Application__event_0__Application__event_0
ENDCASERAND
CASERAND 50
WRITE DIPLODOCUS_C_Design__channel_0 1
WRITE Application__channel_0 1
ENDCASERAND
ENDRAND
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp2
TASK Application__PrimitiveComp2
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
WAIT DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event
WAIT Application__event__Application__event
ENDCASERAND
CASERAND 50
READ DIPLODOCUS_C_Design__channel 1
READ Application__channel 1
ENDCASERAND
ENDRAND
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp2_0
TASK Application__PrimitiveComp2_0
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
WAIT DIPLODOCUS_C_Design__event_0__DIPLODOCUS_C_Design__event_0
WAIT Application__event_0__Application__event_0
ENDCASERAND
CASERAND 50
READ DIPLODOCUS_C_Design__channel_0 1
READ Application__channel_0 1
ENDCASERAND
ENDRAND
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp3
TASK Application__PrimitiveComp3
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel2 1
WRITE Application__channel2 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp3_0
TASK Application__PrimitiveComp3_0
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel2_0 1
WRITE Application__channel2_0 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp4
TASK Application__PrimitiveComp4
TASKOP
//Local variables
//Behavior
READ DIPLODOCUS_C_Design__channel2 1
READ Application__channel2 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp4_0
TASK Application__PrimitiveComp4_0
TASKOP
//Local variables
//Behavior
READ DIPLODOCUS_C_Design__channel2_0 1
READ Application__channel2_0 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp5
TASK Application__PrimitiveComp5
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel3 1
WRITE Application__channel3 1
READ Application__channel3 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp5_0
TASK Application__PrimitiveComp5_0
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel3_0 1
WRITE Application__channel3_0 1
READ Application__channel3_0 1
ENDTASK
TASK Application__PrimitiveComp6
TASKOP
//Local variables
//Behavior
WRITE Application__channel4 1
READ Application__channel4 1
ENDTASK
ttool/src/test/resources/tmltranslator/expected/expected_spec2.tarchi 0 → 100644
+ 72
− 0
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// Master clock frequency - in MHz
MASTERCLOCKFREQUENCY 200
NODE DMA DMA0
SET DMA0 byteDataSize 4
SET DMA0 nbOfChannels 1
NODE BUS Bus0
SET Bus0 byteDataSize 4
SET Bus0 pipelineSize 1
SET Bus0 arbitration 0
NODE MEMORY Memory0
SET Memory0 byteDataSize 4
NODE CPU CPU0
SET CPU0 nbOfCores 1
SET CPU0 byteDataSize 4
SET CPU0 pipelineSize 5
SET CPU0 goIdleTime 10
SET CPU0 maxConsecutiveIdleCycles 10
SET CPU0 taskSwitchingTime 20
SET CPU0 branchingPredictionPenalty 2
SET CPU0 cacheMiss 5
SET CPU0 schedulingPolicy 0
SET CPU0 sliceTime 10000
SET CPU0 execiTime 1
SET CPU0 execcTime 1
SET CPU0 operation
NODE CPU CPU2
SET CPU2 nbOfCores 1
SET CPU2 byteDataSize 4
SET CPU2 pipelineSize 5
SET CPU2 goIdleTime 10
SET CPU2 maxConsecutiveIdleCycles 10
SET CPU2 taskSwitchingTime 20
SET CPU2 branchingPredictionPenalty 2
SET CPU2 cacheMiss 5
SET CPU2 schedulingPolicy 0
SET CPU2 sliceTime 10000
SET CPU2 execiTime 1
SET CPU2 execcTime 1
SET CPU2 operation
NODE CPU CPU1
SET CPU1 nbOfCores 1
SET CPU1 byteDataSize 4
SET CPU1 pipelineSize 5
SET CPU1 goIdleTime 10
SET CPU1 maxConsecutiveIdleCycles 10
SET CPU1 taskSwitchingTime 20
SET CPU1 branchingPredictionPenalty 2
SET CPU1 cacheMiss 5
SET CPU1 schedulingPolicy 0
SET CPU1 sliceTime 10000
SET CPU1 execiTime 1
SET CPU1 execcTime 1
SET CPU1 operation
NODE LINK link_CPU0_to_Bus0
SET link_CPU0_to_Bus0 node CPU0
SET link_CPU0_to_Bus0 bus Bus0
SET link_CPU0_to_Bus0 priority 0
NODE LINK link_Memory0_to_Bus0
SET link_Memory0_to_Bus0 node Memory0
SET link_Memory0_to_Bus0 bus Bus0
SET link_Memory0_to_Bus0 priority 0
NODE LINK link_DMA0_to_Bus0
SET link_DMA0_to_Bus0 node DMA0
SET link_DMA0_to_Bus0 bus Bus0
SET link_DMA0_to_Bus0 priority 0
\ No newline at end of file
ttool/src/test/resources/tmltranslator/expected/expected_spec2.tml
+ 37
− 25
View file @ 970be8cd
// TML Application - FORMAT 0.1
// Application: /home/pham/Documents/TToolHelp/TTool/modeling/DIPLODOCUS/CloneCompositeComponentTest.xml
// Generated: Wed Mar 20 17:20:10 CET 2019
// Generated: Thu Mar 21 16:19:37 CET 2019
// Channels
CHANNEL DIPLODOCUS_C_Design__channel BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp1 IN DIPLODOCUS_C_Design__PrimitiveComp2
CHANNEL DIPLODOCUS_C_Design__channel2 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp3 IN DIPLODOCUS_C_Design__PrimitiveComp4
CHANNEL DIPLODOCUS_C_Design__channel2_0 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp3_0 IN DIPLODOCUS_C_Design__PrimitiveComp4_0
CHANNEL DIPLODOCUS_C_Design__channel3 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp5 IN DIPLODOCUS_C_Design__PrimitiveComp5
CHANNEL DIPLODOCUS_C_Design__channel3_0 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp5_0 IN DIPLODOCUS_C_Design__PrimitiveComp5_0
CHANNEL Application__channel BRBW 4 8 OUT Application__PrimitiveComp1 IN Application__PrimitiveComp2
CHANNEL Application__channel2 BRBW 4 8 OUT Application__PrimitiveComp3 IN Application__PrimitiveComp4
CHANNEL Application__channel2_0 BRBW 4 8 OUT Application__PrimitiveComp3_0 IN Application__PrimitiveComp4_0
CHANNEL Application__channel3 BRBW 4 8 OUT Application__PrimitiveComp5 IN Application__PrimitiveComp5
CHANNEL Application__channel3_0 BRBW 4 8 OUT Application__PrimitiveComp5_0 IN Application__PrimitiveComp5_0
CHANNEL Application__channel4 BRBW 4 8 OUT Application__PrimitiveComp6 IN Application__PrimitiveComp6
// Events
EVENT DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event() NIB 8 DIPLODOCUS_C_Design__PrimitiveComp1 DIPLODOCUS_C_Design__PrimitiveComp2
EVENT Application__event__Application__event() NIB 8 Application__PrimitiveComp1 Application__PrimitiveComp2
// Requests
TASK DIPLODOCUS_C_Design__PrimitiveComp1
TASK Application__PrimitiveComp1
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
NOTIFY DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event
NOTIFY Application__event__Application__event
ENDCASERAND
CASERAND 50
WRITE DIPLODOCUS_C_Design__channel 1
WRITE Application__channel 1
ENDCASERAND
ENDRAND
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp2
TASK Application__PrimitiveComp2
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
WAIT DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event
WAIT Application__event__Application__event
ENDCASERAND
CASERAND 50
READ DIPLODOCUS_C_Design__channel 1
READ Application__channel 1
ENDCASERAND
ENDRAND
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp3
TASK Application__PrimitiveComp3
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel2 1
WRITE Application__channel2 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp3_0
TASK Application__PrimitiveComp3_0
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel2_0 1
WRITE Application__channel2_0 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp4
TASK Application__PrimitiveComp4
TASKOP
//Local variables
//Behavior
READ DIPLODOCUS_C_Design__channel2 1
READ Application__channel2 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp4_0
TASK Application__PrimitiveComp4_0
TASKOP
//Local variables
//Behavior
READ DIPLODOCUS_C_Design__channel2_0 1
READ Application__channel2_0 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp5
TASK Application__PrimitiveComp5
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel3 1
WRITE Application__channel3 1
READ Application__channel3 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp5_0
TASK Application__PrimitiveComp5_0
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel3_0 1
WRITE Application__channel3_0 1
READ Application__channel3_0 1
ENDTASK
TASK Application__PrimitiveComp6
TASKOP
//Local variables
//Behavior
WRITE Application__channel4 1
READ Application__channel4 1
ENDTASK
ttool/src/test/resources/tmltranslator/expected/expected_spec3.tml
+ 32
− 20
View file @ 970be8cd
// TML Application - FORMAT 0.1
// Application: /home/pham/Documents/TToolHelp/TTool/modeling/DIPLODOCUS/CloneCompositeComponentTest.xml
// Generated: Wed Mar 20 17:20:50 CET 2019
// Generated: Thu Mar 21 16:20:51 CET 2019
// Channels
CHANNEL DIPLODOCUS_C_Design__channel BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp1 IN DIPLODOCUS_C_Design__PrimitiveComp2
CHANNEL DIPLODOCUS_C_Design__channel2 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp3 IN DIPLODOCUS_C_Design__PrimitiveComp4
CHANNEL DIPLODOCUS_C_Design__channel3 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp5 IN DIPLODOCUS_C_Design__PrimitiveComp5
CHANNEL DIPLODOCUS_C_Design__channel3_0 BRBW 4 8 OUT DIPLODOCUS_C_Design__PrimitiveComp5_0 IN DIPLODOCUS_C_Design__PrimitiveComp5_0
CHANNEL Application__channel BRBW 4 8 OUT Application__PrimitiveComp1 IN Application__PrimitiveComp2
CHANNEL Application__channel2 BRBW 4 8 OUT Application__PrimitiveComp3 IN Application__PrimitiveComp4
CHANNEL Application__channel3 BRBW 4 8 OUT Application__PrimitiveComp5 IN Application__PrimitiveComp5
CHANNEL Application__channel3_0 BRBW 4 8 OUT Application__PrimitiveComp5_0 IN Application__PrimitiveComp5_0
CHANNEL Application__channel4 BRBW 4 8 OUT Application__PrimitiveComp6 IN Application__PrimitiveComp6
// Events
EVENT DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event() NIB 8 DIPLODOCUS_C_Design__PrimitiveComp1 DIPLODOCUS_C_Design__PrimitiveComp2
EVENT Application__event__Application__event() NIB 8 Application__PrimitiveComp1 Application__PrimitiveComp2
// Requests
TASK DIPLODOCUS_C_Design__PrimitiveComp1
TASK Application__PrimitiveComp1
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
NOTIFY DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event
NOTIFY Application__event__Application__event
ENDCASERAND
CASERAND 50
WRITE DIPLODOCUS_C_Design__channel 1
WRITE Application__channel 1
ENDCASERAND
ENDRAND
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp2
TASK Application__PrimitiveComp2
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
WAIT DIPLODOCUS_C_Design__event__DIPLODOCUS_C_Design__event
WAIT Application__event__Application__event
ENDCASERAND
CASERAND 50
READ DIPLODOCUS_C_Design__channel 1
READ Application__channel 1
ENDCASERAND
ENDRAND
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp3
TASK Application__PrimitiveComp3
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel2 1
WRITE Application__channel2 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp4
TASK Application__PrimitiveComp4
TASKOP
//Local variables
//Behavior
READ DIPLODOCUS_C_Design__channel2 1
READ Application__channel2 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp5
TASK Application__PrimitiveComp5
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel3 1
WRITE Application__channel3 1
READ Application__channel3 1
ENDTASK
TASK DIPLODOCUS_C_Design__PrimitiveComp5_0
TASK Application__PrimitiveComp5_0
TASKOP
//Local variables
//Behavior
WRITE DIPLODOCUS_C_Design__channel3_0 1
WRITE Application__channel3_0 1
READ Application__channel3_0 1
ENDTASK
TASK Application__PrimitiveComp6
TASKOP
//Local variables
//Behavior
WRITE Application__channel4 1
READ Application__channel4 1
ENDTASK
ttool/src/test/resources/tmltranslator/expected/expected_spec4.tml 0 → 100644
+ 88
− 0
View file @ 970be8cd
// TML Application - FORMAT 0.1
// Application: /home/pham/Documents/TToolHelp/TTool/modeling/DIPLODOCUS/CloneCompositeComponentTest.xml
// Generated: Thu Mar 21 16:24:12 CET 2019
// Channels
CHANNEL Application__channel BRBW 4 8 OUT Application__PrimitiveComp1 IN Application__PrimitiveComp2
CHANNEL Application__channel2 BRBW 4 8 OUT Application__PrimitiveComp3 IN Application__PrimitiveComp4
CHANNEL Application__channel3 BRBW 4 8 OUT Application__PrimitiveComp5 IN Application__PrimitiveComp5
CHANNEL Application__channel4 BRBW 4 8 OUT Application__PrimitiveComp6 IN Application__PrimitiveComp6
CHANNEL Application__channel4_0 BRBW 4 8 OUT Application__PrimitiveComp6_0 IN Application__PrimitiveComp6_0
// Events
EVENT Application__event__Application__event() NIB 8 Application__PrimitiveComp1 Application__PrimitiveComp2
// Requests
TASK Application__PrimitiveComp1
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
NOTIFY Application__event__Application__event
ENDCASERAND
CASERAND 50
WRITE Application__channel 1
ENDCASERAND
ENDRAND
ENDTASK
TASK Application__PrimitiveComp2
TASKOP
//Local variables
//Behavior
RAND
CASERAND 50
WAIT Application__event__Application__event
ENDCASERAND
CASERAND 50
READ Application__channel 1
ENDCASERAND
ENDRAND
ENDTASK
TASK Application__PrimitiveComp3
TASKOP
//Local variables
//Behavior
WRITE Application__channel2 1
ENDTASK
TASK Application__PrimitiveComp4
TASKOP
//Local variables
//Behavior
READ Application__channel2 1
ENDTASK
TASK Application__PrimitiveComp5
TASKOP
//Local variables
//Behavior
WRITE Application__channel3 1
READ Application__channel3 1
ENDTASK
TASK Application__PrimitiveComp6
TASKOP
//Local variables
//Behavior
WRITE Application__channel4 1
READ Application__channel4 1
ENDTASK
TASK Application__PrimitiveComp6_0
TASKOP
//Local variables
//Behavior
WRITE Application__channel4_0 1
READ Application__channel4_0 1
ENDTASK
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