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Commit f3519246 authored by apvrille's avatar apvrille
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Update on clone comp test

parent 291c78d2
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ttool/src/test/resources/tmltranslator/expected/expected_spec1.tmap
+ 9
− 9
View file @ f3519246
......@@ -9,14 +9,14 @@ ENDTMLARCHI
TMLMAPPING
MAP CPU0 Application__PrimitiveComp1
SET Application__PrimitiveComp1 priority 0
MAP CPU0 Application__PrimitiveComp6
SET Application__PrimitiveComp6 priority 0
MAP CPU0 Application__PrimitiveComp5
SET Application__PrimitiveComp5 priority 0
MAP CPU0 Application__PrimitiveComp4
SET Application__PrimitiveComp4 priority 0
MAP CPU0 Application__PrimitiveComp3
SET Application__PrimitiveComp3 priority 0
MAP CPU0 Application__PrimitiveComp2
SET Application__PrimitiveComp2 priority 0
ENDTMLMAPPING
\ No newline at end of file
MAP CPU0 Application__PrimitiveComp3
SET Application__PrimitiveComp3 priority 0
MAP CPU0 Application__PrimitiveComp4
SET Application__PrimitiveComp4 priority 0
MAP CPU0 Application__PrimitiveComp5
SET Application__PrimitiveComp5 priority 0
MAP CPU0 Application__PrimitiveComp6
SET Application__PrimitiveComp6 priority 0
ENDTMLMAPPING
ttool/src/test/resources/tmltranslator/expected/expected_spec2.tarchi
+ 1
− 1
View file @ f3519246
......@@ -72,4 +72,4 @@ SET link_Memory0_to_Bus0 priority 0
NODE LINK link_DMA0_to_Bus0
SET link_DMA0_to_Bus0 node DMA0
SET link_DMA0_to_Bus0 bus Bus0
SET link_DMA0_to_Bus0 priority 0
\ No newline at end of file
SET link_DMA0_to_Bus0 priority 0
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