Commits · 58168102bce8c41282c90d211e0abf8c6d9a8535 · mbe-tools / TTool

Jun 14, 2019
- Slight update on simulator · 58168102
  apvrille authored 5 years ago
  
  58168102
Jun 07, 2019
- Update on simulation traces · 6fea1fe5
  Ludovic Apvrille authored 5 years ago
  
  6fea1fe5
- Removing useless cout in diplo simulator · a4dcb3db
  Ludovic Apvrille authored 5 years ago
  
  a4dcb3db
Jun 06, 2019
- Adding params of events in txt and html traces · fefe4fb3
  apvrille authored 5 years ago
  
  fefe4fb3
Jun 04, 2019
- css ok and delete commits · 9619fbeb
  Siyuan Niu authored 5 years ago
  
  9619fbeb
Jun 03, 2019
- First complete simulation · c3b3f751
  apvrille authored 5 years ago
  
  c3b3f751
- Simulation of tonetwork: ok · 5d44159e
  apvrille authored 5 years ago
  
  5d44159e
- Update on simulator debug and task bug in tonetwork · ea19b491
  Ludovic Apvrille authored 5 years ago
  
  ea19b491
May 21, 2019
- vcd ok · 47a31dc5
  Siyuan Niu authored 5 years ago
  
  47a31dc5
- html file ok execpt the name · 7ebbc50b
  Siyuan Niu authored 5 years ago
  
  7ebbc50b
- pie chart location ok · 046be899
  Siyuan Niu authored 5 years ago
  
  046be899
- task name ok · bba70ef5
  Siyuan Niu authored 5 years ago
  
  bba70ef5
- tasks distribute ok · b9dc394c
  Siyuan Niu authored 5 years ago
  
  b9dc394c
May 20, 2019
- html change · af41fd3a
  Siyuan Niu authored 5 years ago
  
  af41fd3a
May 17, 2019
- simulator seems ok · 4869fee2
  Siyuan Niu authored 5 years ago
  
  4869fee2
May 13, 2019
- fpga simulator ok · 7615c6b9
  Siyuan Niu authored 5 years ago
  
  7615c6b9
- fpga not ok · 3264afbd
  Siyuan Niu authored 5 years ago
  
  3264afbd
- Update on simulator:revert to working version · f1bda6a9
  apvrille authored 5 years ago
  
  f1bda6a9
- Update on FPGA: xml with ID · b39798b9
  apvrille authored 5 years ago
  
  b39798b9
May 10, 2019
- fpga smartcard · 0be8fa3e
  Siyuan Niu authored 5 years ago
  
  0be8fa3e
- fpga smartcard seems ok · 018d8a49
  Siyuan Niu authored 5 years ago
  
  018d8a49
- fpga my complex model ok but smartcard not ok · 1d33d266
  Siyuan Niu authored 5 years ago
  
  1d33d266
May 09, 2019
- html for fpga is ok · b5862f5c
  Siyuan Niu authored 5 years ago
  
  b5862f5c
May 07, 2019
- 4tasks 2fpgas communication ok · fdb49eec
  Siyuan Niu authored 5 years ago
  
  fdb49eec
May 02, 2019
- 2tasks 2fpgas communication ok · 062085b4
  Siyuan Niu authored 5 years ago
  
  062085b4
- several tasks on one fpga ok, 2 fpga not ok · a31cb004
  Siyuan Niu authored 5 years ago
  
  a31cb004
Apr 30, 2019
- Resolving bug on transaction displaying · 017393d8
  Ludovic Apvrille authored 5 years ago
  
  017393d8
Apr 29, 2019
- add files ok · 862422c4
  Siyuan Niu authored 5 years ago
  
  862422c4
- smartcard is ok · 0cb106ec
  Siyuan Niu authored 5 years ago
  
  0cb106ec
Apr 26, 2019
- Reverting to a working simulator · 8fee20bb
  Ludovic Apvrille authored 5 years ago
  
  8fee20bb
- add cpu.cpp · 16a0afea
  Siyuan Niu authored 5 years ago
  
  16a0afea
- add fpga but fpga is not correct · dde79bc5
  Siyuan Niu authored 5 years ago
  
  dde79bc5
- circular diagram ok · 73b73e16
  Siyuan Niu authored 5 years ago
  
  73b73e16
Apr 24, 2019
- tab cell is ok · a5cd59b1
  Siyuan Niu authored 5 years ago
  
  a5cd59b1
Apr 18, 2019
- commit before change TMLTask to TMLTaskCPU and TMLTaskFPGA · 2d2f1f13
  Siyuan Niu authored 5 years ago
  
  2d2f1f13
Apr 17, 2019
- load and percentage is ok · f04adbc4
  Siyuan Niu authored 5 years ago
  
  f04adbc4
- commit to change branch · 3b8893f7
  Siyuan Niu authored 5 years ago
  
  3b8893f7
Apr 11, 2019
- change html model name · 34e2930f
  Siyuan Niu authored 5 years ago
  
  34e2930f
Apr 10, 2019
- html model name and vcd change · b49cd333
  Siyuan Niu authored 5 years ago
  
  b49cd333
Apr 09, 2019
- change html file core name and information · 98e8b653
  Siyuan Niu authored 5 years ago
  
  98e8b653