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mbe-tools
TTool
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e72481dbcb11b8ab47a05f8acfad79301b65d530
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20
113-firewall-action-in-diplodocus-adds-a-non-visible-element
117-nightly-build-graphic-installer-window-not-resizeable
126-order-of-tabs-in-diplodocus-component-models-is-not-preserved
155-update-developper-documentation
157-installer-does-not-work-under-windows-and-linux
242-gui-automated-test-second-part
244-merging-zoom-branch
2stepApproach
31-zoom-on-all-diagrams
69-allow-to-be-able-to-disable-action-nodes-in-an-activity-diagram
71-gui-automated-tests
71-gui-automated-tests-2
71-gui-automated-tests-3
73-hidden-component-still-clickable
73-hidden-component-still-clickable-2
73-hidden-component-still-clickable-3
78-forbidden-identifiers
AIMULET
AMULETPatches
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20 results
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Created with Raphaël 2.2.0
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update on build version: build.txt
update on build version: build.txt
Merge branch 'fpga_sim_change' into 'master'
simulator seems ok
fpga_sim_change
fpga_sim_change
Update on SVG capture
update on build version: build.txt
Update on code generation: adding orderscheduler
NEw code generator for FPGAs
fpga simple mode vcd is ok
fpga_vcd
fpga_vcd
Update for FPGA systemC code generation. Still not working
Merge branch 'master' of gitlab.enst.fr:mbe-tools/TTool
Update on FPGA management in tmldd
added models for testing synchronous and asynchronous signaling
small problem of no penalty for fpga
name for fpga and task is ok
task vcd is ok without penalty
update on build version: build.txt
Updated CP reconfig method + created test and test model
cp_config_updat…
cp_config_update cp_reconfigure
Update on router handling
deleted model test in diplodocus repo
updated test
updatePort_mapp…
updatePort_mapped_in_CPNode
Created model for test
Merge branch 'master' of gitlab.enst.fr:mbe-tools/TTool
Merge branch 'master' of gitlab.enst.fr:mbe-tools/TTool
Solving bugs on network gen
Adding filter for ttool help
vcd ok part
updated cp node config for DMA and FPGA node
update on build version: build.txt
Update on help
Corrected DMA node type (from Transfer to Controller)
Merge branch 'master' of gitlab.enst.fr:mbe-tools/TTool
Update on TMLMapping parsing
Created method for the reconfiguration of CP nodes after renaming HW node names
update on build version: build.txt
Update on TTool help
Update on Help HTML and button in jadialogcpu
Created test and test model for port mapping
Merge branch 'fpga_change_simulator' into 'master'
fpga simulator ok
fpga_change_sim…
fpga_change_simulator
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