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Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
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16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive
Updated
Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive