Commit 3346857f authored by Daniela Genius's avatar Daniela Genius
Browse files

topcell generation

parent 77c13763
/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
* Daniela Genius, Lip6, UMR 7606
*
* ludovic.apvrille AT enst.fr
* daniela.genius@lip6.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*/
/* authors: v1.0 Raja GATGOUT 2014
v2.0 Daniela GENIUS, Julien HENON 2015
v2.1 Daniela GENIUS, 2016, 2017 */
package ddtranslatorSoclib.toTopCell;
import ddtranslatorSoclib.*;
import avatartranslator.AvatarRelation;
import avatartranslator.AvatarBlock;
import avatartranslator.AvatarSignal;
import avatartranslator.AvatarSpecification;
public class Declaration {
public static AvatarSpecification avspec;
private static String CR = "\n";
private static String CR2 = "\n\n";
public static String generateName(AvatarRelation _ar, int _index) {
return _ar.block1.getName() + "_" + _ar.getSignal1(_index).getName() + "__" + _ar.block2.getName() + "_" + _ar.getSignal2(_index).getName();
}
public static String getDeclarations(AvatarSpecification _avspec) {
avspec =_avspec;
String declaration = "//----------------------------Instantiation-------------------------------" + CR2;
int nb_clusters = TopCellGenerator.avatardd.getAllCrossbar().size();
boolean trace_caba=true;
if(nb_clusters==0){
declaration += CR
+ "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0), maptab);" + CR;
}
else{
declaration += CR
+ "caba::VciHeterogeneousRom<vci_param> vcihetrom(\"vcihetrom\", IntTab(0,0), maptab);" + CR;
}
if(nb_clusters==0){
declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(1), maptab, data_ldr);" + CR;
}
else{
declaration += "caba::VciRam<vci_param> vcirom(\"vcirom\", IntTab(0,1), maptab, data_ldr);" + CR;
}
if(nb_clusters==0){
declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(3), maptab);" + CR;
}
else{
declaration += " caba::VciSimhelper<vci_param> vcisimhelper (\"vcisimhelper\", IntTab(0,3), maptab);" + CR;
}
if(nb_clusters==0){
declaration = declaration + "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(4), 1, xicu_n_irq, cpus.size(), cpus.size());" + CR;
}
else{
declaration = declaration + "caba::VciXicu<vci_param> vcixicu(\"vci_xicu\", maptab, IntTab(0,4), 1, xicu_n_irq, cpus.size(), cpus.size());" + CR;
}
if(nb_clusters==0){
declaration = declaration + "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(5), maptab, 1, true);" + CR2;
}
else{
declaration = declaration + "caba::VciRtTimer<vci_param> vcirttimer (\"vcirttimer\", IntTab(0,5), maptab, 1, true);" + CR2;
}
if(nb_clusters==0){
declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(6), maptab);" + CR;
}
else{
declaration += "caba::VciFdtRom<vci_param> vcifdtrom(\"vci_fdt_rom\", IntTab(0,6), maptab);" + CR;
}
if(nb_clusters==0){
declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab("+(TopCellGenerator.avatardd.getNb_target()+3)+"), maptab);" + CR;
}
else{
declaration += "caba::VciLocks<vci_param> vcilocks(\"vcilocks\", IntTab(0,8), maptab);" + CR;
}
if(nb_clusters==0){
int i=0;
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName()+ "(\"" + tty.getTTYName()+ "\", IntTab(" + tty.getNo_target()+ "), maptab, \"vci_multi_tty"+i+"\", NULL);"+ CR;
i++;
}
//target address depends on number of TTYs and RAMs
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
if(ram.getIndex()==0){
declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab(2), maptab);" + CR;
}
else{
declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab("
+ ram.getNo_target() + "), maptab);" + CR;
}
}
else{
int i=0;
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
declaration += "caba::VciMultiTty<vci_param> " + tty.getTTYName()+ "(\"" + tty.getTTYName()+ "\", IntTab("+ tty.getNo_cluster()+"," + tty.getNo_target()+ "), maptab, \"vci_multi_tty"+i+"\", NULL);"+ CR;
i++;}
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
declaration += "soclib::caba::VciRam<vci_param>" + ram.getMemoryName()+ "(\"" + ram.getMemoryName()+ "\"" + ", IntTab("+ram.getNo_cluster()+","
+ ram.getNo_target() + "), maptab);" + CR2;
}
if(nb_clusters==0){
declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(cpus.size()+1), IntTab("+(TopCellGenerator.avatardd.getNb_target())+"));" + CR;
declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(cpus.size()+2), IntTab("+(TopCellGenerator.avatardd.getNb_target()+1)+"), \"soclib0\");" + CR;
declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(cpus.size()), IntTab("+(TopCellGenerator.avatardd.getNb_target()+2)+"),\"block0.iso\", 2048);" + CR;
}else{
declaration += "caba::VciFdAccess<vci_param> vcifd(\"vcifd\", maptab, IntTab(0,cpus.size()+1), IntTab(0,7));" + CR;
declaration += "caba::VciEthernet<vci_param> vcieth(\"vcieth\", maptab, IntTab(0,cpus.size()+2), IntTab(0,8), \"soclib0\");" + CR;
declaration += "caba::VciBlockDevice<vci_param> vcibd(\"vcibd\", maptab, IntTab(0,cpus.size()), IntTab(0,9),\"block0.iso\", 2048);" + CR;
}
if(nb_clusters==0){
for (AvatarBus bus : TopCellGenerator.avatardd.getAllBus()) {
System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
//declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+");" + CR2;
declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ ");" + CR2;
int i=0;
//if BUS was not last in input file, update here
bus.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
bus.setnbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target());
}
for (AvatarVgmn vgmn : TopCellGenerator.avatardd.getAllVgmn()) {
//System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
//System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
/* The user might have forgotten to specify the following, thus set default values */
if(vgmn.getMinLatency()<2)
vgmn.setMinLatency(10); //default value; must be > 2
if(vgmn.getFifoDepth()<2)
vgmn.setFifoDepth(8); //default value; must be > 2
//declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNb_target()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
declaration += "soclib::caba::VciVgmn<vci_param> vgmn(\"" + vgmn.getVgmnName() + "\"" + " , maptab, cpus.size()+3," + (TopCellGenerator.avatardd.getNbRAM()+TopCellGenerator.avatardd.getNbTTY()+4)+ "," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
// if VGMN was not last in input file, update here
vgmn.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
vgmn.setnbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target()+4);
}
/* VciMwmrController(
sc_module_name name,
const MappingTable &mt,
const IntTab &srcid,
const IntTab &tgtid,
const size_t plaps,
const size_t fifo_to_coproc_depth,
const size_t fifo_from_coproc_depth,
const size_t n_to_coproc,
const size_t n_from_coproc,
const size_t n_config,
const size_t n_status,
const bool use_llsc );
*/
//only non-clustered version
for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
declaration += "caba::VciMwmrController<vci_param> " + copro.getCoprocName()+ "(\"" + copro.getCoprocName()+ "\", maptab, IntTab("+copro.getSrcid() + "), IntTab("+copro.getTgtid() + "),copro.getPlaps(),copro.getFifoToCoProcDepth(),copro.getNToCopro(),copro.getNFromCopro(),copro.getNConfig(),copro.getNStatus(), copro.getUseLLSC());"+ CR;
}
}
else {
/***************************************/
/* clustered interconnect architecture */
/***************************************/
for (AvatarBus bus : TopCellGenerator.avatardd.getAllBus()) {
declaration += "soclib::caba::VciVgsb<vci_param> vgsb(\"" + bus.getBusName() + "\"" + " , maptab, "+ +nb_clusters+"," + nb_clusters + ");" + CR2;
//if BUS was not last in input file, update here
int i=0;
}
for (AvatarVgmn vgmn : TopCellGenerator.avatardd.getAllVgmn()) {
System.out.println("initiators: "+TopCellGenerator.avatardd.getNb_init());
System.out.println("targets: "+TopCellGenerator.avatardd.getNb_target());
declaration += "soclib::caba::VciVgmn<vci_param> vgmn (\"" + vgmn.getVgmnName() + "\"" + " , maptab, "+ nb_clusters +"," + nb_clusters +
"," + vgmn.getMinLatency() + "," + vgmn.getFifoDepth() + ");" + CR2;
}
int i=0;
for (AvatarCrossbar crossbar : TopCellGenerator.avatardd.getAllCrossbar()) {
//currently the number on initiators and targets is fixed
crossbar.setClusterIndex(i);
if (crossbar.getClusterIndex()==0){
crossbar.setNbOfAttachedInitiators(nb_clusters);
crossbar.setNbOfAttachedTargets(13);
}
else{
//processor(s) and link to central interconnect are initiators
//crossbar.setNbOfAttachedInitiators(2);
//crossbar.setNbOfAttachedTargets(2);
crossbar.setNbOfAttachedInitiators(1);
crossbar.setNbOfAttachedTargets(1);
}
System.out.println("initiators: "+crossbar.getNbOfAttachedInitiators());
System.out.println("targets: "+crossbar.getNbOfAttachedTargets());
declaration += "soclib::caba::VciLocalCrossbar<vci_param> crossbar"+crossbar.getClusterIndex()+"(\"" + crossbar.getCrossbarName() + "\"" + " , maptab, IntTab("+ crossbar.getClusterIndex()+"),IntTab("+crossbar.getClusterIndex()+"), "+crossbar.getNbOfAttachedInitiators()+", "+crossbar.getNbOfAttachedTargets()+");" + CR2;
//if CROSSBAR was not last in input file, update here
crossbar.setNbOfAttachedInitiators(TopCellGenerator.avatardd.getNb_init());
crossbar.setNbOfAttachedTargets(TopCellGenerator.avatardd.getNb_target());
}
}
int i=0;
//monitoring CPU by logger(1)
for (AvatarCPU cpu : TopCellGenerator.avatardd.getAllCPU()) {
if (cpu.getMonitored()==1){
System.out.println("Spy CPU");
declaration += "soclib::caba::VciLogger<vci_param> logger"+i+"(\"logger" + i+"\",maptab);" + CR2;
i++;
}
}
int j=0;
//monitoring RAM either by logger(1) ou stats (2)
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM()) {
if (ram.getMonitored()==0){
}
if (ram.getMonitored()==1){
System.out.println("Spy RAM : Logger");
declaration += "soclib::caba::VciLogger<vci_param> logger"+i+"(\"logger" + i+"\",maptab);" + CR2;
i++;
}
else{
if (ram.getMonitored()==2){
System.out.println("Spy RAM : Stats");
String strArray="";
for(AvatarRelation ar: avspec.getRelations()) {
for(i=0; i<ar.nbOfSignals() ; i++) {
AvatarSignal as1=ar.getSignal1(i);
AvatarSignal as2=ar.getSignal2(i);
String chname = generateName(ar,i);
strArray=strArray+"\""+chname+"\",";
}
}
declaration += "soclib::caba::VciMwmrStats<vci_param> mwmr_stats"+j+"(\"mwmr_stats" + j+"\",maptab, data_ldr, \"mwmr"+j+".log\",stringArray("+strArray+"NULL));" + CR2;
j++;
}
}
}
return declaration;
}
}
\ No newline at end of file
/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
* Daniela Genius, Lip6, UMR 7606
*
* ludovic.apvrille AT enst.fr
* daniela.genius@lip6.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*/
/* this class produces the lines containing essentially the initial #includes; we include all potential components event if they are not used in the deployment diagram*/
/* authors: v1.0 Raja GATGOUT 2014
v2.0 Daniela GENIUS, Julien HENON 2015 */
package ddtranslatorSoclib.toTopCell;
public class Header {
static private String header;
int nb_clusters=5;
private final static String CR = "\n";
private final static String CR2 = "\n\n";
Header(){
}
public static String getHeader() {
int with_vgsb=TopCellGenerator.avatardd.getAllBus().size();
header = "//-------------------------------Header------------------------------------" + CR2
+ "#include <iostream>" + CR
+ "#include <cstdlib>" + CR
+ "#include <vector>" + CR
+ "#include <string>" + CR
+ "#include <stdexcept>" + CR
+ "#include <cstdarg>" +CR2
+ "#define CONFIG_GDB_SERVER" + CR
+ "#define CONFIG_SOCLIB_MEMCHECK" + CR2;
header = header + "#include \"iss_memchecker.h\"" + CR
+"#include \"gdbserver.h\""+ CR2
+"#include \"ppc405.h\"" + CR
+"#include \"niosII.h\"" + CR
+"#include \"mips32.h\"" + CR
+"#include \"arm.h\"" + CR
+"#include \"sparcv8.h\"" + CR
+"#include \"lm32.h\"" + CR2
+ "#include \"mapping_table.h\"" + CR
+ "#include \"vci_fdt_rom.h\"" + CR + "#include \"vci_xcache_wrapper.h\"" + CR
+ "#include \"vci_ram.h\"" + CR + "#include \"vci_heterogeneous_rom.h\"" + CR
+ "#include \"vci_multi_tty.h\"" + CR + "#include \"vci_locks.h\"" + CR + "#include \"vci_xicu.h\""+ CR
+ "#include \"vci_mwmr_stats.h\""+ CR;//DG 20.09.
if (with_vgsb>0){
header +="#include \"vci_vgsb.h\""+ CR;
}
else{
header +="#include \"vci_vgmn.h\""+ CR;
}
header+= "#include \"vci_block_device.h\"" + CR
+ "#include \"vci_simhelper.h\"" + CR + "#include \"vci_fd_access.h\"" + CR
+ "#include \"vci_ethernet.h\"" + CR
+ "#include \"vci_rttimer.h\"" + CR
+ "#include \"vci_logger.h\"" + CR
+ "#include \"vci_local_crossbar.h\"" + CR2;
header = header +"namespace {" + CR
+"std::vector<std::string> stringArray(" + CR
+" const char *first, ... )" + CR
+"{" + CR
+" std::vector<std::string> ret;" + CR
+" va_list arg;" + CR
+" va_start(arg, first);" + CR
+" const char *s = first;" + CR
+" while(s) {" + CR
+" ret.push_back(std::string(s));" + CR
+" s = va_arg(arg, const char *);" + CR
+" };" + CR
+" va_end(arg);" + CR
+" return ret;" + CR
+"}" + CR2
+"std::vector<int> intArray(" + CR
+" const int length, ... )" + CR
+"{" + CR
+" int i;" + CR
+" std::vector<int> ret;" + CR
+" va_list arg;" + CR
+" va_start(arg, length);" + CR2
+" for (i=0; i<length; ++i) {" + CR
+" ret.push_back(va_arg(arg, int));" + CR
+" };" + CR
+" va_end(arg);" + CR
+" return ret;" + CR
+"}" + CR
+"}" + CR2;
header = header + "using namespace soclib;" + CR + "using common::IntTab;" + CR + "using common::Segment;";
if(TopCellGenerator.avatardd.getNbClusters()==0){
header = header + CR2 + "static common::MappingTable maptab(32, IntTab(8), IntTab(8), 0xfff00000);";
}
else{
header = header + CR2 + "static common::MappingTable maptab(32, IntTab(8,4), IntTab(8,4), 0xfff00000);";
}
return header;
}
}
This diff is collapsed.
/* Copyright or (C) or Copr. GET / ENST, Telecom-Paris, Ludovic Apvrille
* Daniela Genius, Lip6, UMR 7606
*
* ludovic.apvrille AT enst.fr
* daniela.genius@lip6.fr
*
* This software is a computer program whose purpose is to allow the
* edition of TURTLE analysis, design and deployment diagrams, to
* allow the generation of RT-LOTOS or Java code from this diagram,
* and at last to allow the analysis of formal validation traces
* obtained from external tools, e.g. RTL from LAAS-CNRS and CADP
* from INRIA Rhone-Alpes.
*
* This software is governed by the CeCILL license under French law and
* abiding by the rules of distribution of free software. You can use,
* modify and/ or redistribute the software under the terms of the CeCILL
* license as circulated by CEA, CNRS and INRIA at the following URL
* "http://www.cecill.info".
*
* As a counterpart to the access to the source code and rights to copy,
* modify and redistribute granted by the license, users are provided only
* with a limited warranty and the software's author, the holder of the
* economic rights, and the successive licensors have only limited
* liability.
*
* In this respect, the user's attention is drawn to the risks associated
* with loading, using, modifying and/or developing or reproducing the
* software by the user in light of its specific status of free software,
* that may mean that it is complicated to manipulate, and that also
* therefore means that it is reserved for developers and experienced
* professionals having in-depth computer knowledge. Users are therefore
* encouraged to load and test the software's suitability as regards their
* requirements in conditions enabling the security of their systems and/or
* data to be ensured and, more generally, to use and operate it in the
* same conditions as regards security.
*
* The fact that you are presently reading this means that you have had
* knowledge of the CeCILL license and that you accept its terms.
*/
/* This class generates the lines of the topcell where the signals are declared*/
/* authors: v1.0 Raja GATGOUT 2014
v2.0 Daniela GENIUS, Julien HENON 2015 */
package ddtranslatorSoclib.toTopCell;
import ddtranslatorSoclib.AvatarCoproMWMR;
import ddtranslatorSoclib.AvatarRAM;
import ddtranslatorSoclib.AvatarTTY;
public class Signal {
private final static String CR = "\n";
private final static String CR2 = "\n\n";
private final static String NAME_CLK = "signal_clk";
private static final String NAME_RST = "signal_resetn";
public static String getSignal() {
int nb_clusters=TopCellGenerator.avatardd.getAllCrossbar().size();
//nb_clusters=2;
String signal = CR2 + "//-------------------------------signaux------------------------------------" + CR2;
signal = signal + "caba::VciSignals<vci_param> signal_vci_m[cpus.size() + 1];"+ CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_xicu(\"signal_vci_xicu\");"+ CR;
signal = signal + "caba::VciSignals<vci_param> signal_vci_vcifdtrom(\"signal_vci_vcifdtrom\");"+ CR;
signal = signal +" caba::VciSignals<vci_param> signal_vci_vcihetrom(\"signal_vci_vcihetrom\");"+ CR;
signal = signal +" caba::VciSignals<vci_param> signal_vci_vcirom(\"signal_vci_vcirom\");"+ CR;
signal = signal +" caba::VciSignals<vci_param> signal_vci_vcisimhelper(\"signal_vci_vcisimhelper\");"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_vcirttimer(\"signal_vci_vcirttimer\");"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_vcilocks(\"signal_vci_vcilocks\");"+ CR;
//signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmr_ram(\"signal_vci_mwmr_ram\");"+ CR;
//signal = signal +"caba::VciSignals<vci_param> signal_vci_mwmrd_ram(\"signal_vci_mwmrd_ram\");"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccessi;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_vcifdaccesst;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_bdi;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_bdt;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_etherneti;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_vci_ethernett;"+ CR;
signal = signal +""+ CR;
signal = signal + "sc_clock signal_clk(\"signal_clk\");" + CR;
signal = signal + "sc_signal<bool> signal_resetn(\"" + NAME_RST + "\");" + CR2;
int i=0;
for (AvatarCoproMWMR copro : TopCellGenerator.avatardd.getAllCoproMWMR()){
signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_initiator;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_mwmr_"+i+"_target;"+ CR;
signal = signal +"caba::VciSignals<vci_param> signal_fifo_"+i+"_ctrl;"+ CR;
}
if(TopCellGenerator.avatardd.getAllCrossbar().size()==0){
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2;
i = 0;
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
//signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" + CR2;
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
i++;
}
signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
System.out.print("number of processors : " + TopCellGenerator.avatardd.getNbCPU()+"\n");
}
else{
for (AvatarRAM ram : TopCellGenerator.avatardd.getAllRAM())
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_vciram" + ram.getIndex()
+ "(\"signal_vci_vciram" + ram.getIndex() + "\");" + CR2; i=0;
for (AvatarTTY tty : TopCellGenerator.avatardd.getAllTTY()){
// signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+tty.getNo_tty()+"(\"signal_vci_tty"+tty.getNo_tty()+"\");" + CR2;
signal = signal + "soclib::caba::VciSignals<vci_param> signal_vci_tty"+i+"(\"signal_vci_tty"+i+"\");" + CR2;
i++;
}
signal = signal + " sc_core::sc_signal<bool> signal_xicu_irq[xicu_n_irq];" + CR2;
//System.out.print("number of processors : " + TopCellGenerator.avatardd.getNbCPU()+"\n");
System