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add divider clock value to FPGA
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- simulators/c++2/src_simulator/arch/FPGA.cpp 11 additions, 9 deletionssimulators/c++2/src_simulator/arch/FPGA.cpp
- simulators/c++2/src_simulator/arch/FPGA.h 2 additions, 1 deletionsimulators/c++2/src_simulator/arch/FPGA.h
- src/main/java/tmltranslator/tomappingsystemc2/DiploSimulatorCodeGenerator.java 1 addition, 1 deletion...slator/tomappingsystemc2/DiploSimulatorCodeGenerator.java
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