Created test for cloning mapping and architecture node

ttool/src/test/java/ui/TDiagramPanelCloneArchitectureTest.java

+package ui;
+
+import myutil.TraceManager;
+import org.junit.*;
+import tmltranslator.compareTMLTest.CompareTML;
+import ui.tmldd.TMLArchiDiagramPanel;
+
+import java.io.*;
+
+import static org.junit.Assert.*;
+/*
+ * #issue 186
+ * author : Minh Hiep
+ */
+public class TDiagramPanelCloneArchitectureTest extends AbstractUITest {
+    
+    static TDiagramPanel architecture;
+    static  TGComponent cpu1;
+
+    static TGComponent mapChannel;
+
+
+    final static String EXPECTED_FILE1 = getBaseResourcesDir() + "tmltranslator/expected/expected_spec1.tmap";
+    final static String EXPECTED_FILE2 = getBaseResourcesDir() + "tmltranslator/expected/expected_spec2.tarchi";
+
+
+    @BeforeClass
+    public static void setUpBeforeClass() throws Exception {
+        RESOURCES_DIR = getBaseResourcesDir() + "/ui/diagram2tml/input/CloneCompositeComponentTest.xml";
+    }
+
+    public TDiagramPanelCloneArchitectureTest() {
+        super();
+        mainGUI.openProjectFromFile(new File(RESOURCES_DIR));
+    }
+
+    @Before
+    public void setUp() {
+        architecture = null;
+        for(TURTLEPanel _tab : mainGUI.getTabs()) {
+            if(_tab instanceof TMLArchiPanel) {
+                for (TDiagramPanel tdp : _tab.getPanels()) {
+                    if (tdp instanceof TMLArchiDiagramPanel) {
+                        architecture = tdp;
+                        mainGUI.selectTab(architecture);
+                        break;
+                    }
+                }
+                break;
+            }
+        }
+
+        if (architecture != null) {
+            //TraceManager.addDev("architecture tab is non null");
+            for (TGComponent tgc : architecture.getAllComponentList()) {
+                if (tgc.getValue().equals("Application::PrimitiveComp1")) {
+                    mapChannel = tgc;
+                }
+
+                if (tgc.getName().equals("CPU1")) {
+                    cpu1 = tgc;
+                }
+            }
+        }
+    }
+
+    @Test
+    public void testCloneMapInArchitecture() throws Exception {
+        CompareTML compTML = new CompareTML();
+        TGComponent mapTaskClone = null;
+        architecture.cloneComponent(mapChannel);
+        architecture.removeComponent(mapChannel);
+        for (TGComponent tgc : architecture.getComponentList()) {
+            if (tgc.getValue().equals("Application::PrimitiveComp1")) {
+                mapTaskClone = tgc;
+            }
+        }
+
+        if (mapTaskClone != null) {
+            //TraceManager.addDev("mapTaskClone is non null");
+            architecture.attach(mapTaskClone);
+        }
+        mainGUI.checkModelingSyntax(true);
+        mainGUI.generateTMLTxt();
+        File f1 = new File(EXPECTED_FILE1);
+        File f2 = new File("spec.tmap");  // Generated file after executing "TML generation"
+        assertTrue(compTML.compareTML(f1,f2));
+    }
+
+    @Test
+    public void testCloneNodeInArchitecture() throws Exception {
+        CompareTML compTML = new CompareTML();
+        architecture.cloneComponent(cpu1);
+        for (TGComponent tgc : architecture.getComponentList()) {
+            if (tgc.getName().equals("CPU1")) {
+                tgc.setName("CPU2");
+                break;
+            }
+        }
+
+        mainGUI.checkModelingSyntax(true);
+        mainGUI.generateTMLTxt();
+        File f1 = new File(EXPECTED_FILE2);
+        File f2 = new File("spec.tarchi");  // Generated file after executing "TML generation"
+        assertTrue(compTML.compareTML(f1,f2));
+    }
+
+
+}
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ttool/src/test/resources/tmltranslator/expected/expected_spec1.tmap

+TMLSPEC
+    #include "spec.tml"
+ENDTMLSPEC
+
+TMLARCHI
+    #include "spec.tarchi"
+ENDTMLARCHI
+
+TMLMAPPING
+    MAP CPU0 Application__PrimitiveComp1
+    SET Application__PrimitiveComp1 priority 0
+    MAP CPU0 Application__PrimitiveComp6
+    SET Application__PrimitiveComp6 priority 0
+    MAP CPU0 Application__PrimitiveComp5
+    SET Application__PrimitiveComp5 priority 0
+    MAP CPU0 Application__PrimitiveComp4
+    SET Application__PrimitiveComp4 priority 0
+    MAP CPU0 Application__PrimitiveComp3
+    SET Application__PrimitiveComp3 priority 0
+    MAP CPU0 Application__PrimitiveComp2
+    SET Application__PrimitiveComp2 priority 0
+ENDTMLMAPPING
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ttool/src/test/resources/tmltranslator/expected/expected_spec2.tarchi

+// Master clock frequency - in MHz
+MASTERCLOCKFREQUENCY 200
+
+NODE DMA DMA0
+SET DMA0 byteDataSize 4
+SET DMA0 nbOfChannels 1
+
+NODE BUS Bus0
+SET Bus0 byteDataSize 4
+SET Bus0 pipelineSize 1
+SET Bus0 arbitration 0
+
+NODE MEMORY Memory0
+SET Memory0 byteDataSize 4
+
+NODE CPU CPU0
+SET CPU0 nbOfCores 1
+SET CPU0 byteDataSize 4
+SET CPU0 pipelineSize 5
+SET CPU0 goIdleTime 10
+SET CPU0 maxConsecutiveIdleCycles 10
+SET CPU0 taskSwitchingTime 20
+SET CPU0 branchingPredictionPenalty 2
+SET CPU0 cacheMiss 5
+SET CPU0 schedulingPolicy 0
+SET CPU0 sliceTime 10000
+SET CPU0 execiTime 1
+SET CPU0 execcTime 1
+SET CPU0 operation
+
+NODE CPU CPU2
+SET CPU2 nbOfCores 1
+SET CPU2 byteDataSize 4
+SET CPU2 pipelineSize 5
+SET CPU2 goIdleTime 10
+SET CPU2 maxConsecutiveIdleCycles 10
+SET CPU2 taskSwitchingTime 20
+SET CPU2 branchingPredictionPenalty 2
+SET CPU2 cacheMiss 5
+SET CPU2 schedulingPolicy 0
+SET CPU2 sliceTime 10000
+SET CPU2 execiTime 1
+SET CPU2 execcTime 1
+SET CPU2 operation
+
+NODE CPU CPU1
+SET CPU1 nbOfCores 1
+SET CPU1 byteDataSize 4
+SET CPU1 pipelineSize 5
+SET CPU1 goIdleTime 10
+SET CPU1 maxConsecutiveIdleCycles 10
+SET CPU1 taskSwitchingTime 20
+SET CPU1 branchingPredictionPenalty 2
+SET CPU1 cacheMiss 5
+SET CPU1 schedulingPolicy 0
+SET CPU1 sliceTime 10000
+SET CPU1 execiTime 1
+SET CPU1 execcTime 1
+SET CPU1 operation
+
+NODE LINK link_CPU0_to_Bus0
+SET link_CPU0_to_Bus0 node CPU0
+SET link_CPU0_to_Bus0 bus Bus0
+SET link_CPU0_to_Bus0 priority 0
+NODE LINK link_Memory0_to_Bus0
+SET link_Memory0_to_Bus0 node Memory0
+SET link_Memory0_to_Bus0 bus Bus0
+SET link_Memory0_to_Bus0 priority 0
+NODE LINK link_DMA0_to_Bus0
+SET link_DMA0_to_Bus0 node DMA0
+SET link_DMA0_to_Bus0 bus Bus0
+SET link_DMA0_to_Bus0 priority 0
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