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RAMSES-2 (Refinement of AADL Models for Synthesis of Embedded Systems) is a model refinement and code generation tool that produces C code for ARINC653, OSEK and POSIX-compliant operating systems. More at https://mem4csd.telecom-paristech.fr/blog/

Présentation de l'offre de service de la DSI

A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

Fork from https://gitlab.inf.telecom-sudparis.eu/infra-web/hotcrp-docker.git

A toy example project showing how GitLab CI can be used for teaching

Various small projects by Renaud Pacalet

TD équation de Kaya, transition énergétique et développement durable

A hardware / software architecture protecting the external memories of an SoC

This is a project of OPC UA specification Part 14 PubSub implementation.

The project include 2 major parts : OPC UA server with opc ua pubsub kit and OPC UA MQTT Configuration tool .