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QoE testbed for sampling constrained applications like Skype

A simple example design for Zynq Ultrascale+ based boards.

SystemVerilog simulation environment for an UART

16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive

Matlab implementation associated with the article "On the use and denoising of the temporal geometric mean for SAR time series", submitted to IEEE Geoscience and Remote sensing Letters by N.Gasnier, L.Denis and F.Tupin.

A hardware / software architecture protecting the external memories of an SoC

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

TD équation de Kaya, transition énergétique et développement durable

Various small projects by Renaud Pacalet

A toy example project showing how GitLab CI can be used for teaching

Yet another Makefile for LaTeX