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Nouveau thème Beamer aux couleur de Télécom Paris

Nouveau thème Beamer aux couleur de Télécom Paris

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

A simple example design for Zynq Ultrascale+ based boards.

TD équation de Kaya, transition énergétique et développement durable

16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive

SystemVerilog simulation environment for an UART

QoE testbed for sampling constrained applications like Skype

A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

Yet another Makefile for LaTeX

Matlab implementation associated with the article "On the use and denoising of the temporal geometric mean for SAR time series", submitted to IEEE Geoscience and Remote sensing Letters by N.Gasnier, L.Denis and F.Tupin.