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A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

Generic flow table implementation

A hardware / software architecture protecting the external memories of an SoC

Embb, a generic hardware and software architecture for digital signal processing

RAMSES-2 (Refinement of AADL Models for Synthesis of Embedded Systems) is a model refinement and code generation tool that produces C code for ARINC653, OSEK and POSIX-compliant operating systems. More at https://mem4csd.telecom-paristech.fr/blog/

SAR Image Despeckling by Deep Neural Networks: from a pre-trained model to an end-to-end training strategy - Notebook implementation usable on Google Colaboratory

Code archive for the paper Does Functional Package Management Enable Reproducible Builds at Scale? Yes.

QoE testbed for sampling constrained applications like Skype

Model synchronization between Adele and OSATE with MoTE TGG.