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Generic flow table implementation

Yet another Makefile for LaTeX

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

Nouveau thème Beamer aux couleur de Télécom Paris

TD équation de Kaya, transition énergétique et développement durable

Nouveau thème Beamer aux couleur de Télécom Paris

A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

A hardware / software architecture protecting the external memories of an SoC

Matlab implementation associated with the article "On the use and denoising of the temporal geometric mean for SAR time series", submitted to IEEE Geoscience and Remote sensing Letters by N.Gasnier, L.Denis and F.Tupin.