Explore projects

TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paris.fr and @TTool_UML_SysML

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

Embb, a generic hardware and software architecture for digital signal processing

Generation of SystemC code from AADL models for functional simulation

This is a project of OPC UA specification Part 14 PubSub implementation.

The project include 2 major parts : OPC UA server with opc ua pubsub kit and OPC UA MQTT Configuration tool .