Explore GitLab
Discover projects, groups and snippets. Share your projects with others
-
-
-
-
QoE testbed for sampling constrained applications like Skype
-
Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
-
-
A perl utility to send data acquired by a sensor, through an Ethernet link (UDP packets), to a remote computer for real-time visualization with Gnuplot
-
A simple example design for Zynq Ultrascale+ based boards.
-
A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.
Xilinx Zynq VHDL Linux+ 2 more -
-
-
-
TP!!!!!!!!
-
-
-
A set of scripts and Makefiles for digital hardware projects
-
-
-
-
simple python script to convert Synapses csv schedules to ics calendars.