QoE testbed for sampling constrained applications like Skype
Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
A simple example design for Zynq Ultrascale+ based boards.
Embb, a generic hardware and software architecture for digital signal processing
Model synchronization between Adele and OSATE with MoTE TGG.
This is a project of OPC UA specification Part 14 PubSub implementation.
The project include 2 major parts : OPC UA server with opc ua pubsub kit and OPC UA MQTT Configuration tool .
This project contains the ontological framework developed during the MPM4CPS COST Action IC1404 () by working group 1 on foundations for MPM4CPS (http://mpm4cps.eu/).