Explore projects

A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.

QoE testbed for sampling constrained applications like Skype

Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator

A simple example design for Zynq Ultrascale+ based boards.

TP!!!!!!!!

Embb, a generic hardware and software architecture for digital signal processing

Model synchronization between Adele and OSATE with MoTE TGG.

This is a project of OPC UA specification Part 14 PubSub implementation.

The project include 2 major parts : OPC UA server with opc ua pubsub kit and OPC UA MQTT Configuration tool .