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TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paris.fr and @TTool_UML_SysML
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RAMSES (Refinement of AADL Models for Synthesis of Embedded Systems) is a model transformation and code generation tool that produces C code for ARINC653-compliant operating systems and OSEK-compliant operating systems.
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Modèle pour la génération de supports de cours (poly+slides) au format html, pdf et même docx à partir d'une source unique (au format markdown/pandooc).
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simple python script to convert Synapses csv schedules to ics calendars.
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Modified version of QEMU for teaching (M2 SETI Embedded Linux, SE758 Linux Device Drivers...).
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This is a project of OPC UA specification Part 14 PubSub implementation.
The project include 2 major parts : OPC UA server with opc ua pubsub kit and OPC UA MQTT Configuration tool .
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Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
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