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Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
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sdram20 / MCsimCoq
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sdram20 / coqdram
Apache License 2.0Updated -
Xuecan Yang / darknet_mnist
MIT LicenseUpdated -
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16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive
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Cédric Ware / cours.td-kaya
Creative Commons Attribution-NonCommercial-ShareAlike 2.0 FranceTD équation de Kaya, transition énergétique et développement durable
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Renaud Pacalet / sab4u
CeCILL Free Software License Agreement v2.1A simple example design for Zynq Ultrascale+ based boards.
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QoE testbed for sampling constrained applications like Skype
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Renaud Pacalet / sab4z
CeCILL Free Software License Agreement v2.1A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.
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Renaud Pacalet / mli
CeCILL Free Software License Agreement v2.1Yet another Makefile for LaTeX
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ring / Geometric_Mean_Denoising
CeCILL Free Software License Agreement v2.0Matlab implementation associated with the article "On the use and denoising of the temporal geometric mean for SAR time series", submitted to IEEE Geoscience and Remote sensing Letters by N.Gasnier, L.Denis and F.Tupin.
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