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A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.
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A toy example project showing how GitLab CI can be used for teaching
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TD équation de Kaya, transition énergétique et développement durable
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Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
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A hardware / software architecture protecting the external memories of an SoC
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Matlab implementation associated with the article "On the use and denoising of the temporal geometric mean for SAR time series", submitted to IEEE Geoscience and Remote sensing Letters by N.Gasnier, L.Denis and F.Tupin.
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