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16 nibbles (64 bits) parallel sboxes using Xilinx CFGLUT5 primitive
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Matlab implementation associated with the article "On the use and denoising of the temporal geometric mean for SAR time series", submitted to IEEE Geoscience and Remote sensing Letters by N.Gasnier, L.Denis and F.Tupin.
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Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
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A hardware / software architecture protecting the external memories of an SoC
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