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Modèle pour la génération de supports de cours (poly+slides) au format html, pdf et même docx à partir d'une source unique (au format markdown/pandooc).
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RAMSES (Refinement of AADL Models for Synthesis of Embedded Systems) is a model transformation and code generation tool that produces C code for ARINC653-compliant operating systems and OSEK-compliant operating systems.
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TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paris.fr and @TTool_UML_SysML
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This project provides utility libraries that can be used by several MBE tools such as RAMSES, TTool or RDALTE
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A simple example design for Zynq-based boards. VHDL design of custom HW mapped in Programmable Logic, Linux - Busybox - Buildroot SW stack, user SW applications interacting with custom hardware, Linux drivers, SW and HW debugging.
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Example of Verilog/SystemVerilog + SystemC TB simulation using Verilator
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Embb, a generic hardware and software architecture for digital signal processing
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