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TTool (pronounced "tea-tool") is a toolkit dedicated to the edition of UML and SysML diagrams, and to the simulation and formal verification (safety, security, performance) of those diagrams. See ttool.telecom-paris.fr and @TTool_UML_SysML
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Experiment Specification (ExSpec) is a language to specify the provenance of experiment/simulation data. ExSpec models are the basis of the Validity Frame Language (VaFL, pronounced "waffle") to specify the validity frames of models.
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This project provides utility libraries that can be used by several MBE tools such as RAMSES, TTool or RDALTE
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RAMSES-2 (Refinement of AADL Models for Synthesis of Embedded Systems) is a model refinement and code generation tool that produces C code for ARINC653, OSEK and POSIX-compliant operating systems. More at https://mem4csd.telecom-paristech.fr/blog/
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A Benchmark of Incremental Model Transformation Tools based on an Industrial Case Study with AADL
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Generation of SystemC code from AADL models for functional simulation
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